[PATCH] D107880: [AArch64][SVE] Remove assertion/range check for i16 values during immediate selection

[Eli Friedman via Phabricator via llvm-commits]

efriedma accepted this revision.
efriedma added a comment.
This revision is now accepted and ready to land.

LGTM with one minor change.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:3154
         return true;
       } else if ((ImmVal & 0xFF) == 0) {
         Shift = CurDAG->getTargetConstant(8, DL, MVT::i32);
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I think the way lowering currently works, we currently don't have any guarantee at all about what the high bits of ImmVal contain; this follows from the definition of SPLAT_VECTOR.  So probably we should be explicitly masking off the high bits.  I doubt that has any practical effect here, though; just deleting the assertion is probably good enough.


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Comment at: llvm/test/CodeGen/AArch64/sve-int-arith-imm.ll:806
+;
+define <vscale x 8 x i16> @uqsub(<vscale x 8 x i16> %a) {
+; CHECK-LABEL: uqsub:
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Please stick this next to the other tests in llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith-imm.ll .


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D107880/new/

https://reviews.llvm.org/D107880