[PATCH] D107657: [RISCV][VP] Add support for VP_REDUCE_* operations

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:2115
+SDValue DAGTypeLegalizer::PromoteIntOp_VP_REDUCE(SDNode *N, unsigned OpNo) {
+  SDLoc DL(N);
+  SDValue Op = PromoteIntOpVectorReduction(N, N->getOperand(OpNo));
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craig.topper wrote:
> What values of OpNo do we expect here? 0 shouldn't happen since it was handled in result promotion. 1 clearly will happen. I'm not sure about 2 and 3, but using PromoteIntOpVectorReduction for them would be incorrect.
Yeah you're right, thanks. I think 0 is out of the runnings after the latest round of changes. I don't think we can get 3 because EVL is promoted early to a target-specific type which is assumed/required to be legal.

So yeah, looking at the handling of `MGATHER` I think I need to update this function to handle the mask at `OpNo` 2. We won't have tests for it but I can maybe manufacture something locally to make sure it's not obviously bad.


Repository:
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  https://reviews.llvm.org/D107657/new/

https://reviews.llvm.org/D107657