[PATCH] D107657: [RISCV][VP] Add support for VP_REDUCE_* operations

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:2115
+SDValue DAGTypeLegalizer::PromoteIntOp_VP_REDUCE(SDNode *N, unsigned OpNo) {
+  SDLoc DL(N);
+  SDValue Op = PromoteIntOpVectorReduction(N, N->getOperand(OpNo));
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What values of OpNo do we expect here? 0 shouldn't happen since it was handled in result promotion. 1 clearly will happen. I'm not sure about 2 and 3, but using PromoteIntOpVectorReduction for them would be incorrect.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D107657/new/

https://reviews.llvm.org/D107657