[llvm] 7cbcde4 - [M68k] Use separate asm operand class for different widths of address
Min-Yih Hsu via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 9 00:08:37 PDT 2021
Author: Min-Yih Hsu
Date: 2021-08-09T00:07:19-07:00
New Revision: 7cbcde4aa302135a78417aa0435f9da71a62137d
URL: https://github.com/llvm/llvm-project/commit/7cbcde4aa302135a78417aa0435f9da71a62137d
DIFF: https://github.com/llvm/llvm-project/commit/7cbcde4aa302135a78417aa0435f9da71a62137d.diff
LOG: [M68k] Use separate asm operand class for different widths of address
This could help asm parser to pick the correct variant of instruction.
This patch also migrated all the control instructions MC tests.
Added:
llvm/test/MC/M68k/Control/Classes/MxBRA.s
llvm/test/MC/M68k/Control/Classes/MxBcc.s
llvm/test/MC/M68k/Control/Classes/MxCALL.s
Modified:
llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
llvm/lib/Target/M68k/M68kInstrInfo.td
Removed:
llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxBRA.mir
llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxBcc.mir
llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxCALL.mir
################################################################################
diff --git a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
index bde44d4545d03..1e7854b9b79ea 100644
--- a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
+++ b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
@@ -133,6 +133,8 @@ class M68kOperand : public MCParsedAsmOperand {
M68kMemOp MemOp;
};
+ template <unsigned N> bool isAddrN() const;
+
public:
M68kOperand(enum Kind Kind, SMLoc Start, SMLoc End)
: Base(), Kind(Kind), Start(Start), End(End) {}
@@ -172,6 +174,9 @@ class M68kOperand : public MCParsedAsmOperand {
// Addr
bool isAddr() const;
+ bool isAddr8() const { return isAddrN<8>(); }
+ bool isAddr16() const { return isAddrN<16>(); }
+ bool isAddr32() const { return isAddrN<32>(); }
void addAddrOperands(MCInst &Inst, unsigned N) const;
// ARI
@@ -306,6 +311,17 @@ std::unique_ptr<M68kOperand> M68kOperand::createImm(const MCExpr *Expr,
bool M68kOperand::isAddr() const {
return isMemOp() && MemOp.Op == M68kMemOp::Kind::Addr;
}
+// TODO: Maybe we can also store the size of OuterDisp
+// in Size?
+template <unsigned N> bool M68kOperand::isAddrN() const {
+ if (isAddr()) {
+ int64_t Res;
+ if (MemOp.OuterDisp->evaluateAsAbsolute(Res))
+ return isInt<N>(Res);
+ return true;
+ }
+ return false;
+}
void M68kOperand::addAddrOperands(MCInst &Inst, unsigned N) const {
M68kOperand::addExpr(Inst, MemOp.OuterDisp);
}
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.td b/llvm/lib/Target/M68k/M68kInstrInfo.td
index 3825c24f8e5ce..cd22bec2fe5ba 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.td
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.td
@@ -165,9 +165,11 @@ def MxSize8 : MxSize<8, "b", "byte">;
def MxSize16 : MxSize<16, "w", "word">;
def MxSize32 : MxSize<32, "l", "long">;
-class MxOpClass<string name> : AsmOperandClass {
+class MxOpClass<string name,
+ list<AsmOperandClass> superClasses = []> : AsmOperandClass {
let Name = name;
let ParserMethod = "parseMemOp";
+ let SuperClasses = superClasses;
}
def MxRegClass : MxOpClass<"Reg">;
@@ -176,7 +178,7 @@ def MxRegClass : MxOpClass<"Reg">;
// both ADD32dd and ADD32dr has {MCK_RegClass, MCK_RegClass} for
// their operands, which makes AsmParser unable to pick the correct
// one in a deterministic way.
-let RenderMethod = "addRegOperands", SuperClasses = [MxRegClass] in {
+let RenderMethod = "addRegOperands", SuperClasses = [MxRegClass]in {
def MxARegClass : MxOpClass<"AReg">;
def MxDRegClass : MxOpClass<"DReg">;
}
@@ -317,9 +319,17 @@ def MxARII32_TC : MxMemOp<(ops i8imm, AR32_TC, XR32_TC), MxSize32, "f", "printA
// extended before it is used. The reference is classified as a data reference
// with the exception of the jump and jump-tosubroutine instructions.
def MxAddr : MxOpClass<"Addr">;
-def MxAS8 : MxMemOp<(ops OtherVT), MxSize8, "B", "printAS8Mem", MxAddr>;
-def MxAS16 : MxMemOp<(ops OtherVT), MxSize16, "B", "printAS16Mem", MxAddr>;
-def MxAS32 : MxMemOp<(ops OtherVT), MxSize32, "B", "printAS32Mem", MxAddr>;
+let RenderMethod = "addAddrOperands" in {
+ // This hierarchy ensures Addr8 will always be parsed
+ // before other larger-width variants.
+ def MxAddr32 : MxOpClass<"Addr32", [MxAddr]>;
+ def MxAddr16 : MxOpClass<"Addr16", [MxAddr32]>;
+ def MxAddr8 : MxOpClass<"Addr8", [MxAddr16]>;
+}
+
+def MxAS8 : MxMemOp<(ops OtherVT), MxSize8, "B", "printAS8Mem", MxAddr8>;
+def MxAS16 : MxMemOp<(ops OtherVT), MxSize16, "B", "printAS16Mem", MxAddr16>;
+def MxAS32 : MxMemOp<(ops OtherVT), MxSize32, "B", "printAS32Mem", MxAddr32>;
// ABSOLUTE LONG ADDRESS. This addressing mode requires two words of extension.
// The address of the operand is developed by the concatenation of the extension
@@ -327,9 +337,9 @@ def MxAS32 : MxMemOp<(ops OtherVT), MxSize32, "B", "printAS32Mem", MxAddr>;
// order part of the address is the second extension word. The reference is
// classified as a data reference with the exception of the jump and jump
// to-subroutine instructions.
-def MxAL8 : MxMemOp<(ops OtherVT), MxSize8, "b", "printAL8Mem", MxAddr>;
-def MxAL16 : MxMemOp<(ops OtherVT), MxSize16, "b", "printAL16Mem", MxAddr>;
-def MxAL32 : MxMemOp<(ops OtherVT), MxSize32, "b", "printAL32Mem", MxAddr>;
+def MxAL8 : MxMemOp<(ops OtherVT), MxSize8, "b", "printAL8Mem", MxAddr8>;
+def MxAL16 : MxMemOp<(ops OtherVT), MxSize16, "b", "printAL16Mem", MxAddr16>;
+def MxAL32 : MxMemOp<(ops OtherVT), MxSize32, "b", "printAL32Mem", MxAddr32>;
def MxPCD : MxOpClass<"PCD">;
def MxPCI : MxOpClass<"PCI">;
@@ -383,16 +393,15 @@ def Mxi16imm : MxOp<i16, MxSize16, "i">;
def Mxi32imm : MxOp<i32, MxSize32, "i">;
} // OPERAND_IMMEDIATE
-let OperandType = "OPERAND_PCREL",
- ParserMatchClass = MxAddr,
- PrintMethod = "printPCRelImm" in {
-
+class MxBrTargetOperand<int N> : Operand<OtherVT> {
+ let OperandType = "OPERAND_PCREL";
+ let PrintMethod = "printPCRelImm";
+ let ParserMatchClass = !cast<AsmOperandClass>("MxAddr"#N);
+}
// Branch targets have OtherVT type and print as pc-relative values.
-def MxBrTarget8 : Operand<OtherVT>;
-def MxBrTarget16 : Operand<OtherVT>;
-def MxBrTarget32 : Operand<OtherVT>;
-
-} // OPERAND_PCREL
+def MxBrTarget8 : MxBrTargetOperand<8>;
+def MxBrTarget16 : MxBrTargetOperand<16>;
+def MxBrTarget32 : MxBrTargetOperand<32>;
// Used with MOVEM
def MxMoveMask : MxOp<i16, MxSize16, "m"> {
diff --git a/llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxBRA.mir b/llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxBRA.mir
deleted file mode 100644
index 55f0b37b52a9e..0000000000000
--- a/llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxBRA.mir
+++ /dev/null
@@ -1,49 +0,0 @@
-# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
-# RUN: | extract-section .text \
-# RUN: | FileCheck %s -check-prefixes=BRA8,BRA16
-
-#------------------------------------------------------------------------------
-# MxBRA unconditionally branches somewhere
-#------------------------------------------------------------------------------
-
---- # MxBRA8
-# -------------------------------+-------------------------------
-# F E D C B A 9 8 | 7 6 5 4 3 2 1 0
-# -------------------------------+-------------------------------
-# 0 1 1 0 0 0 0 0 | 8-BIT DISPLACEMENT
-# -------------------------------+-------------------------------
-# BRA8: 0 1 1 0 0 0 0 0 . 0 0 0 0 0 0 0 1
-# BRA8-SAME: 0 1 1 0 0 0 0 0 . 0 0 1 0 1 0 1 0
-#
-# NOTE MxBRA branches cannot encode 0 displacement, 0 in displacement instructs
-# to use additional word. Also it cannot encode -1 since all 1s instruct to use
-# two additional words to encode 32bit offset(since M68020).
-name: MxBRA8
-body: |
- bb.0:
- BRA8 1, implicit $ccr
- BRA8 42, implicit $ccr
-
-...
---- # MxBRA16
-# -------------------------------+-------------------------------
-# F E D C B A 9 8 | 7 6 5 4 3 2 1 0
-# -------------------------------+-------------------------------
-# 0 1 1 0 0 0 0 0 | 0 0 0 0 0 0 0 0
-# ---------------------------------------------------------------
-# BRA16-SAME: 0 1 1 0 0 0 0 0 . 0 0 0 0 0 0 0 0
-# BRA16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
-# -------------------------------+-------------------------------
-# BRA16-SAME: 0 1 1 0 0 0 0 0 . 0 0 0 0 0 0 0 0
-# BRA16-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
-# ---------------------------------------------------------------
-# BRA16-SAME: 0 1 1 0 0 0 0 0 . 0 0 0 0 0 0 0 0
-# BRA16-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0
-name: MxBRA16
-body: |
- bb.0:
- BRA16 0, implicit $ccr
- BRA16 -1, implicit $ccr
- BRA16 42, implicit $ccr
-
-...
diff --git a/llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxBcc.mir b/llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxBcc.mir
deleted file mode 100644
index ef75e35aaf44d..0000000000000
--- a/llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxBcc.mir
+++ /dev/null
@@ -1,126 +0,0 @@
-# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
-# RUN: | extract-section .text \
-# RUN: | FileCheck %s -check-prefixes=BCC8,BLS8,BLT8,BEQ8,BMI8,BNE8,BGE8,BCS8,BPL8
-# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
-# RUN: | extract-section .text \
-# RUN: | FileCheck %s -check-prefixes=BPL8,BGT8,BHI8,BVC8,BLE8,BVS8,BCC16,BLS16
-# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
-# RUN: | extract-section .text \
-# RUN: | FileCheck %s -check-prefixes=BLT16,BEQ16,BMI16,BNE16,BGE16,BCS16,BPL16
-# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
-# RUN: | extract-section .text \
-# RUN: | FileCheck %s -check-prefixes=BGT16,BHI16,BVC16,BLE16,BVS16
-
-#------------------------------------------------------------------------------
-# MxScc branches if the condition is True
-#------------------------------------------------------------------------------
-
---- # MxBcc8
-# ---------------+---------------+-------------------------------
-# F E D C | B A 9 8 | 7 6 5 4 3 2 1 0
-# ---------------+---------------+-------------------------------
-# 0 1 1 0 | CONDITION | 8-BIT DISPLACEMENT
-# ---------------+---------------+-------------------------------
-# BHI8: 0 1 1 0 0 0 1 0 . 0 0 0 0 0 0 0 1
-# BLS8: 0 1 1 0 0 0 1 1 . 0 0 1 0 1 0 1 0
-# BCC8-SAME: 0 1 1 0 0 1 0 0 . 0 0 0 0 0 0 0 1
-# BCS8-SAME: 0 1 1 0 0 1 0 1 . 0 0 0 0 0 0 0 1
-# BNE8-SAME: 0 1 1 0 0 1 1 0 . 0 0 0 0 0 0 0 1
-# BEQ8-SAME: 0 1 1 0 0 1 1 1 . 0 0 0 0 0 0 0 1
-# BVC8-SAME: 0 1 1 0 1 0 0 0 . 0 0 0 0 0 0 0 1
-# BVS8-SAME: 0 1 1 0 1 0 0 1 . 0 0 0 0 0 0 0 1
-# BPL8-SAME: 0 1 1 0 1 0 1 0 . 0 0 0 0 0 0 0 1
-# BMI8-SAME: 0 1 1 0 1 0 1 1 . 0 0 0 0 0 0 0 1
-# BGE8-SAME: 0 1 1 0 1 1 0 0 . 0 0 0 0 0 0 0 1
-# BLT8-SAME: 0 1 1 0 1 1 0 1 . 0 0 0 0 0 0 0 1
-# BGT8-SAME: 0 1 1 0 1 1 1 0 . 0 0 0 0 0 0 0 1
-# BLE8-SAME: 0 1 1 0 1 1 1 1 . 0 0 0 0 0 0 0 1
-#
-# NOTE MxBCC8 branches cannot encode 0 displacement, 0 in displacement instructs
-# to use additional word. Also it cannot encode -1 since all 1s instruct to use
-# two additional words to encode 32bit offset(since M68020).
-name: MxBcc8
-body: |
- bb.0:
- Bhi8 1, implicit $ccr
- Bls8 42, implicit $ccr
- Bcc8 1, implicit $ccr
- Bcs8 1, implicit $ccr
- Bne8 1, implicit $ccr
- Beq8 1, implicit $ccr
- Bvc8 1, implicit $ccr
- Bvs8 1, implicit $ccr
- Bpl8 1, implicit $ccr
- Bmi8 1, implicit $ccr
- Bge8 1, implicit $ccr
- Blt8 1, implicit $ccr
- Bgt8 1, implicit $ccr
- Ble8 1, implicit $ccr
-
-...
---- # MxBcc16
-# ---------------+---------------+-------------------------------
-# F E D C | B A 9 8 | 7 6 5 4 3 2 1 0
-# ---------------+---------------+-------------------------------
-# 0 1 1 0 | CONDITION | 0 0 0 0 0 0 0 0
-# ---------------+---------------+-------------------------------
-# BHI16: 0 1 1 0 0 0 1 0 . 0 0 0 0 0 0 0 0
-# BHI16-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
-# ---------------------------------------------------------------
-# BLS16-SAME: 0 1 1 0 0 0 1 1 . 0 0 0 0 0 0 0 0
-# BLS16-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0
-# ---------------------------------------------------------------
-# BCC16-SAME: 0 1 1 0 0 1 0 0 . 0 0 0 0 0 0 0 0
-# BCC16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
-# ---------------------------------------------------------------
-# BCS16: 0 1 1 0 0 1 0 1 . 0 0 0 0 0 0 0 0
-# BCS16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
-# ---------------------------------------------------------------
-# BNE16-SAME: 0 1 1 0 0 1 1 0 . 0 0 0 0 0 0 0 0
-# BNE16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
-# ---------------------------------------------------------------
-# BEQ16-SAME: 0 1 1 0 0 1 1 1 . 0 0 0 0 0 0 0 0
-# BGE16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
-# ---------------------------------------------------------------
-# BVC16-SAME: 0 1 1 0 1 0 0 0 . 0 0 0 0 0 0 0 0
-# BVC16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
-# ---------------------------------------------------------------
-# BVS16-SAME: 0 1 1 0 1 0 0 1 . 0 0 0 0 0 0 0 0
-# BVS16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
-# ---------------------------------------------------------------
-# BPL16-SAME: 0 1 1 0 1 0 1 0 . 0 0 0 0 0 0 0 0
-# BPL16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
-# ---------------------------------------------------------------
-# BMI16-SAME: 0 1 1 0 1 0 1 1 . 0 0 0 0 0 0 0 0
-# BMI16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
-# ---------------------------------------------------------------
-# BGE16-SAME: 0 1 1 0 1 1 0 0 . 0 0 0 0 0 0 0 0
-# BLE16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
-# ---------------------------------------------------------------
-# BLT16-SAME: 0 1 1 0 1 1 0 1 . 0 0 0 0 0 0 0 0
-# BLT16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
-# ---------------------------------------------------------------
-# BGT16-SAME: 0 1 1 0 1 1 1 0 . 0 0 0 0 0 0 0 0
-# BGT16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
-# ---------------------------------------------------------------
-# BLE16-SAME: 0 1 1 0 1 1 1 1 . 0 0 0 0 0 0 0 0
-# BLE16-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
-name: MxBcc16
-body: |
- bb.0:
- Bhi16 -1, implicit $ccr
- Bls16 42, implicit $ccr
- Bcc16 0, implicit $ccr
- Bcs16 0, implicit $ccr
- Bne16 0, implicit $ccr
- Beq16 0, implicit $ccr
- Bvc16 0, implicit $ccr
- Bvs16 0, implicit $ccr
- Bpl16 0, implicit $ccr
- Bmi16 0, implicit $ccr
- Bge16 0, implicit $ccr
- Blt16 0, implicit $ccr
- Bgt16 0, implicit $ccr
- Ble16 0, implicit $ccr
-
-...
diff --git a/llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxCALL.mir b/llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxCALL.mir
deleted file mode 100644
index bc941237cc79c..0000000000000
--- a/llvm/test/CodeGen/M68k/Encoding/Control/Classes/MxCALL.mir
+++ /dev/null
@@ -1,88 +0,0 @@
-# RUN: llc %s -mtriple=m68k -start-after=prologepilog -O0 -filetype=obj -o - \
-# RUN: | extract-section .text \
-# RUN: | FileCheck %s -check-prefixes=CALLK,CALLQ,CALLB,CALLJ
-
-#------------------------------------------------------------------------------
-# MxCALL pushes address of the next instruction and jumps to the location
-#------------------------------------------------------------------------------
-
---- # MxCALL_PCI
-# ---------------------------------------+-----------+-----------
-# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
-# ---------------------------------------+-----------+-----------
-# 0 1 0 0 1 1 1 0 1 0 | MODE | REG
-# ---------------------------------------+-----------+-----------
-# CALLK: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 1 1
-# CALLK-SAME: 1 0 0 0 1 0 0 0 . 0 0 0 0 0 0 0 0
-# ---------------------------------------+-----------+-----------
-# CALLK-SAME: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 1 1
-# CALLK-SAME: 1 0 0 0 1 0 0 0 . 1 1 1 1 1 1 1 1
-# ---------------------------------------+-----------+-----------
-# CALLK-SAME: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 1 1
-# CALLK-SAME: 1 0 0 0 1 0 0 0 . 0 0 1 0 1 0 1 0
-# ---+-----------+---+-------+---+-------------------------------
-# BRIEF DA | REG | L | SCALE | 0 | DISPLACEMENT
-# ---+-----------+---+-------+---+-------------------------------
-name: MxCALL_PCI
-body: |
- bb.0:
- CALLk 0, $a0
- CALLk -1, $a0
- CALLk 42, $a0
-
-...
---- # MxCALL_PCD
-# ---------------------------------------+-----------+-----------
-# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
-# ---------------------------------------+-----------+-----------
-# 0 1 0 0 1 1 1 0 1 0 | MODE | REG
-# ---------------------------------------+-----------+-----------
-# CALLQ-SAME: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 1 0
-# CALLQ-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
-# ---------------------------------------+-----------+-----------
-# CALLQ-SAME: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 1 0
-# CALLQ-SAME: 0 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
-name: MxCALL_PCD
-body: |
- bb.0:
- CALLq 0
- CALLq 32767
-
-...
---- # MxCALL_ABS
-# ---------------------------------------+-----------+-----------
-# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
-# ---------------------------------------+-----------+-----------
-# 0 1 0 0 1 1 1 0 1 0 | MODE | REG
-# ---------------------------------------+-----------+-----------
-# CALLB-SAME: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 0 1
-# CALLB-SAME: 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 0
-# CALLB-SAME: 0 0 0 0 0 0 0 0 . 0 0 1 0 1 0 1 0
-# ---------------------------------------+-----------+-----------
-# CALLB-SAME: 0 1 0 0 1 1 1 0 . 1 0 1 1 1 0 0 1
-# CALLB-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
-# CALLB-SAME: 1 1 1 1 1 1 1 1 . 1 1 1 1 1 1 1 1
-name: MxCALL_ABS
-body: |
- bb.0:
- CALLb 42
- CALLb -1
-
-...
---- # MxCALL_ARI
-# ---------------------------------------+-----------+-----------
-# F E D C B A 9 8 7 6 | 5 4 3 | 2 1 0
-# ---------------------------------------+-----------+-----------
-# 0 1 0 0 1 1 1 0 1 0 | MODE | REG
-# ---------------------------------------+-----------+-----------
-# CALLJ-SAME: 0 1 0 0 1 1 1 0 . 1 0 0 1 0 0 0 0
-# CALLJ-SAME: 0 1 0 0 1 1 1 0 . 1 0 0 1 0 0 0 1
-# CALLJ-SAME: 0 1 0 0 1 1 1 0 . 1 0 0 1 0 0 1 0
-name: MxCALL_ARI
-body: |
- bb.0:
- CALLj $a0
- CALLj $a1
- CALLj $a2
-
-...
diff --git a/llvm/test/MC/M68k/Control/Classes/MxBRA.s b/llvm/test/MC/M68k/Control/Classes/MxBRA.s
new file mode 100644
index 0000000000000..c8f9d09b291c8
--- /dev/null
+++ b/llvm/test/MC/M68k/Control/Classes/MxBRA.s
@@ -0,0 +1,12 @@
+; RUN: llvm-mc -triple=m68k -motorola-integers -show-encoding %s | FileCheck %s
+
+; CHECK: bra $1
+; CHECK-SAME: encoding: [0x60,0x01]
+bra $1
+; CHECK: bra $2a
+; CHECK-SAME: encoding: [0x60,0x2a]
+bra $2a
+; CHECK: bra $3fc
+; CHECK-SAME: encoding: [0x60,0x00,0x03,0xfc]
+bra $3fc
+
diff --git a/llvm/test/MC/M68k/Control/Classes/MxBcc.s b/llvm/test/MC/M68k/Control/Classes/MxBcc.s
new file mode 100644
index 0000000000000..1e7b7ca48c277
--- /dev/null
+++ b/llvm/test/MC/M68k/Control/Classes/MxBcc.s
@@ -0,0 +1,88 @@
+; RUN: llvm-mc -triple=m68k -motorola-integers -show-encoding %s | FileCheck %s
+
+; CHECK: bhi $1
+; CHECK-SAME: encoding: [0x62,0x01]
+bhi $1
+; CHECK: bls $2a
+; CHECK-SAME: encoding: [0x63,0x2a]
+bls $2a
+; CHECK: bcc $1
+; CHECK-SAME: encoding: [0x64,0x01]
+bcc $1
+; CHECK: bcs $1
+; CHECK-SAME: encoding: [0x65,0x01]
+bcs $1
+; CHECK: bne $1
+; CHECK-SAME: encoding: [0x66,0x01]
+bne $1
+; CHECK: beq $1
+; CHECK-SAME: encoding: [0x67,0x01]
+beq $1
+; CHECK: bvc $1
+; CHECK-SAME: encoding: [0x68,0x01]
+bvc $1
+; CHECK: bvs $1
+; CHECK-SAME: encoding: [0x69,0x01]
+bvs $1
+; CHECK: bpl $1
+; CHECK-SAME: encoding: [0x6a,0x01]
+bpl $1
+; CHECK: bmi $1
+; CHECK-SAME: encoding: [0x6b,0x01]
+bmi $1
+; CHECK: bge $1
+; CHECK-SAME: encoding: [0x6c,0x01]
+bge $1
+; CHECK: blt $1
+; CHECK-SAME: encoding: [0x6d,0x01]
+blt $1
+; CHECK: bgt $1
+; CHECK-SAME: encoding: [0x6e,0x01]
+bgt $1
+; CHECK: ble $1
+; CHECK-SAME: encoding: [0x6f,0x01]
+ble $1
+
+; CHECK: bhi $3fc
+; CHECK-SAME: encoding: [0x62,0x00,0x03,0xfc]
+bhi $3fc
+; CHECK: bls $3fc
+; CHECK-SAME: encoding: [0x63,0x00,0x03,0xfc]
+bls $3fc
+; CHECK: bcc $3fc
+; CHECK-SAME: encoding: [0x64,0x00,0x03,0xfc]
+bcc $3fc
+; CHECK: bcs $3fc
+; CHECK-SAME: encoding: [0x65,0x00,0x03,0xfc]
+bcs $3fc
+; CHECK: bne $3fc
+; CHECK-SAME: encoding: [0x66,0x00,0x03,0xfc]
+bne $3fc
+; CHECK: beq $3fc
+; CHECK-SAME: encoding: [0x67,0x00,0x03,0xfc]
+beq $3fc
+; CHECK: bvc $3fc
+; CHECK-SAME: encoding: [0x68,0x00,0x03,0xfc]
+bvc $3fc
+; CHECK: bvs $3fc
+; CHECK-SAME: encoding: [0x69,0x00,0x03,0xfc]
+bvs $3fc
+; CHECK: bpl $3fc
+; CHECK-SAME: encoding: [0x6a,0x00,0x03,0xfc]
+bpl $3fc
+; CHECK: bmi $3fc
+; CHECK-SAME: encoding: [0x6b,0x00,0x03,0xfc]
+bmi $3fc
+; CHECK: bge $3fc
+; CHECK-SAME: encoding: [0x6c,0x00,0x03,0xfc]
+bge $3fc
+; CHECK: blt $3fc
+; CHECK-SAME: encoding: [0x6d,0x00,0x03,0xfc]
+blt $3fc
+; CHECK: bgt $3fc
+; CHECK-SAME: encoding: [0x6e,0x00,0x03,0xfc]
+bgt $3fc
+; CHECK: ble $3fc
+; CHECK-SAME: encoding: [0x6f,0x00,0x03,0xfc]
+ble $3fc
+
diff --git a/llvm/test/MC/M68k/Control/Classes/MxCALL.s b/llvm/test/MC/M68k/Control/Classes/MxCALL.s
new file mode 100644
index 0000000000000..67dc64e35d543
--- /dev/null
+++ b/llvm/test/MC/M68k/Control/Classes/MxCALL.s
@@ -0,0 +1,36 @@
+; RUN: llvm-mc -triple=m68k -motorola-integers -show-encoding %s | FileCheck %s
+
+; CHECK: jsr (0,%pc,%a0)
+; CHECK-SAME: encoding: [0x4e,0xbb,0x88,0x00]
+jsr (0,%pc,%a0)
+; CHECK: jsr (-1,%pc,%a0)
+; CHECK-SAME: encoding: [0x4e,0xbb,0x88,0xff]
+jsr (-1,%pc,%a0)
+; CHECK: jsr (42,%pc,%a0)
+; CHECK-SAME: encoding: [0x4e,0xbb,0x88,0x2a]
+jsr (42,%pc,%a0)
+
+; CHECK: jsr (0,%pc)
+; CHECK-SAME: encoding: [0x4e,0xba,0x00,0x00]
+jsr (0,%pc)
+; CHECK: jsr (32767,%pc)
+; CHECK-SAME: encoding: [0x4e,0xba,0x7f,0xff]
+jsr (32767,%pc)
+
+; CHECK: jsr $2a
+; CHECK-SAME: encoding: [0x4e,0xb9,0x00,0x00,0x00,0x2a]
+jsr $2a
+; CHECK: jsr $ffffffffffffffff
+; CHECK-SAME: encoding: [0x4e,0xb9,0xff,0xff,0xff,0xff]
+jsr $ffffffffffffffff
+
+; CHECK: jsr (%a0)
+; CHECK-SAME: encoding: [0x4e,0x90]
+jsr (%a0)
+; CHECK: jsr (%a1)
+; CHECK-SAME: encoding: [0x4e,0x91]
+jsr (%a1)
+; CHECK: jsr (%a2)
+; CHECK-SAME: encoding: [0x4e,0x92]
+jsr (%a2)
+
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