[llvm] cf277f0 - [M68k][NFC] Coalesce render methods in different asm register op class

[Min-Yih Hsu via llvm-commits]

Author: Min-Yih Hsu
Date: 2021-08-09T00:07:19-07:00
New Revision: cf277f0b31df14a0800b6cd30c37b76528cdd520

URL: https://github.com/llvm/llvm-project/commit/cf277f0b31df14a0800b6cd30c37b76528cdd520
DIFF: https://github.com/llvm/llvm-project/commit/cf277f0b31df14a0800b6cd30c37b76528cdd520.diff

LOG: [M68k][NFC] Coalesce render methods in different asm register op class

And assign RegClass (i.e. operand class for all GPR) as the super class
of ARegClass and DRegClass. Note that this is a NFC change because
actually we already had XRDReg to model either address or data register
operands (as well as test coverage for it). The new super class syntax
added here is just making the relations between three RegClass-es more
explicit.

Added: 
    

Modified: 
    llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
    llvm/lib/Target/M68k/M68kInstrInfo.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
index e9ce3892dba53..bde44d4545d03 100644
--- a/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
+++ b/llvm/lib/Target/M68k/AsmParser/M68kAsmParser.cpp
@@ -153,12 +153,6 @@ class M68kOperand : public MCParsedAsmOperand {
   bool isDReg() const;
   unsigned getReg() const override;
   void addRegOperands(MCInst &Inst, unsigned N) const;
-  void addARegOperands(MCInst &Inst, unsigned N) const {
-    addRegOperands(Inst, N);
-  }
-  void addDRegOperands(MCInst &Inst, unsigned N) const {
-    addRegOperands(Inst, N);
-  }
 
   static std::unique_ptr<M68kOperand> createMemOp(M68kMemOp MemOp, SMLoc Start,
                                                   SMLoc End);

diff  --git a/llvm/lib/Target/M68k/M68kInstrInfo.td b/llvm/lib/Target/M68k/M68kInstrInfo.td
index e465f256c097b..3825c24f8e5ce 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.td
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.td
@@ -176,8 +176,10 @@ def MxRegClass : MxOpClass<"Reg">;
 // both ADD32dd and ADD32dr has {MCK_RegClass, MCK_RegClass} for
 // their operands, which makes AsmParser unable to pick the correct
 // one in a deterministic way.
-def MxARegClass : MxOpClass<"AReg">;
-def MxDRegClass : MxOpClass<"DReg">;
+let RenderMethod = "addRegOperands", SuperClasses = [MxRegClass] in {
+  def MxARegClass : MxOpClass<"AReg">;
+  def MxDRegClass : MxOpClass<"DReg">;
+}
 
 class MxOperand<ValueType vt, MxSize size, string letter, RegisterClass rc, dag pat = (null_frag)> {
   ValueType VT = vt;