[PATCH] D107068: [DAG] DAGCombiner::visitVECTOR_SHUFFLE - recognise INSERT_SUBVECTOR patterns.

[Benjamin Kramer via llvm-commits]

Test case attached. Crashes with

$ llc < bugpoint-reduced-simplified.ll -mtriple=armv7a-linux-gnu
LLVM ERROR: Cannot select: t73: v4i32 = insert_subvector t71, t69,
Constant:i32<0>
  t71: v4i32 = ARMISD::VMOVIMM TargetConstant:i32<0>
    t28: i32 = TargetConstant<0>
  t69: v2i32 = ARMISD::VMOVIMM TargetConstant:i32<0>
    t28: i32 = TargetConstant<0>
  t3: i32 = Constant<0>

On Fri, Aug 6, 2021 at 10:08 AM Simon Pilgrim via Phabricator via
llvm-commits <llvm-commits at lists.llvm.org> wrote:
>
> RKSimon added a comment.
>
> It looks like ARM is missing the equivalent combine to concat_vectors to AArch64 (or maybe it'll be easier to add isel patterns for neon - I'll have to look), But a test case would be useful please!
>
>
> Repository:
>   rG LLVM Github Monorepo
>
> CHANGES SINCE LAST ACTION
>   https://reviews.llvm.org/D107068/new/
>
> https://reviews.llvm.org/D107068
>
> _______________________________________________
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> llvm-commits at lists.llvm.org
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