[llvm] 7ece205 - [Lanai] fix lowering wide returns

[Fangrui Song via llvm-commits]

Author: Serge Bazanski
Date: 2021-08-05T21:08:09-07:00
New Revision: 7ece20505f12b92d63aa6de0c92d41ac25ab8820

URL: https://github.com/llvm/llvm-project/commit/7ece20505f12b92d63aa6de0c92d41ac25ab8820
DIFF: https://github.com/llvm/llvm-project/commit/7ece20505f12b92d63aa6de0c92d41ac25ab8820.diff

LOG: [Lanai] fix lowering wide returns

This implements LanaiTargetLowering::CanLowerReturn, thereby ensuring
all return values conform to the RetCC and get sret-demoted as
necessary.

A regression test is also added that exercises this functionality.

Reviewed By: jpienaar

Differential Revision: https://reviews.llvm.org/D107086

Added: 
    llvm/test/CodeGen/Lanai/lowering-128.ll

Modified: 
    llvm/lib/Target/Lanai/LanaiISelLowering.cpp
    llvm/lib/Target/Lanai/LanaiISelLowering.h

Removed: 
    


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diff  --git a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
index b96e178109d09..8013fc2fda85b 100644
--- a/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
+++ b/llvm/lib/Target/Lanai/LanaiISelLowering.cpp
@@ -530,6 +530,15 @@ SDValue LanaiTargetLowering::LowerCCCArguments(
   return Chain;
 }
 
+bool LanaiTargetLowering::CanLowerReturn(
+    CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg,
+    const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const {
+  SmallVector<CCValAssign, 16> RVLocs;
+  CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context);
+
+  return CCInfo.CheckReturn(Outs, RetCC_Lanai32);
+}
+
 SDValue
 LanaiTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
                                  bool IsVarArg,

diff  --git a/llvm/lib/Target/Lanai/LanaiISelLowering.h b/llvm/lib/Target/Lanai/LanaiISelLowering.h
index d29d69eaadb05..2f58560f4efe0 100644
--- a/llvm/lib/Target/Lanai/LanaiISelLowering.h
+++ b/llvm/lib/Target/Lanai/LanaiISelLowering.h
@@ -90,6 +90,11 @@ class LanaiTargetLowering : public TargetLowering {
   SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 
+  bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
+                      bool IsVarArg,
+                      const SmallVectorImpl<ISD::OutputArg> &Outs,
+                      LLVMContext &Context) const override;
+
   Register getRegisterByName(const char *RegName, LLT VT,
                              const MachineFunction &MF) const override;
   std::pair<unsigned, const TargetRegisterClass *>

diff  --git a/llvm/test/CodeGen/Lanai/lowering-128.ll b/llvm/test/CodeGen/Lanai/lowering-128.ll
new file mode 100644
index 0000000000000..dbd08095aeac7
--- /dev/null
+++ b/llvm/test/CodeGen/Lanai/lowering-128.ll
@@ -0,0 +1,13 @@
+; RUN: llc -march=lanai < %s | FileCheck %s
+
+; Tests that lowering wide registers (128 bits or more) works on Lanai.
+; The emitted assembly is not checked, we just do a smoketest.
+
+target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
+target triple = "lanai"
+
+; CHECK-LABEL: add128:
+define i128 @add128(i128 %x, i128 %y) {
+  %a = add i128 %x, %y
+  ret i128 %a
+}