[PATCH] D106139: [DAGCombine] Combine srX of add that intends to get the carry as uaddo

Abinav Puthan Purayil via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Aug 5 04:29:04 PDT 2021


abinavpp added a comment.

I pushed the inst-combine version of this at https://reviews.llvm.org/D107552.

In D106139#2910180 <https://reviews.llvm.org/D106139#2910180>, @dmgreen wrote:

> from what I remember instcombine was creating cross-basic-block overflow values, that the backend then couldn't handle very well. I'm not sure that was the exact reason for moving it though, I just remember codesize regressions).

The inst-combine approach had some advantages like: the traversal was depth-first so I can visit the ancestor lshr after the uaddo is generated; I'm concerned with the cross-basic-block overflow use that @dmgreen mentioned above, I could add a bail out check for this since inst-combine works on LLVM-IR and not on a per basic-block DAG like the DAG-combine invoked from SelectionDAGISel::SelectBasicBlock(). But I'm still concerned that we're generating an intrinsic in inst-combine, I couldn't find any TLI.isOperationLegalOrCustom() version in LLVM-IR.


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  https://reviews.llvm.org/D106139/new/

https://reviews.llvm.org/D106139



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