[PATCH] D107512: [AArch64][GlobalISel] Mark v16s8 <- v8s8, v8s8 G_CONCAT_VECTOR as legal

[Amara Emerson via Phabricator via llvm-commits]

aemerson accepted this revision.
aemerson added inline comments.
This revision is now accepted and ready to land.


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Comment at: llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir:86-87
+    ; CHECK: RET_ReallyLR implicit $q0
+    %a:fpr(<8 x s8>) = G_IMPLICIT_DEF
+    %b:fpr(<8 x s8>) = G_IMPLICIT_DEF
+    %concat:fpr(<16 x s8>) = G_CONCAT_VECTORS %a(<8 x s8>), %b(<8 x s8>)
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Can we have real inputs instead of undef? In case we ever optimize this to undef.


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https://reviews.llvm.org/D107512