[PATCH] D107406: [DAGCombiner][TLI] SimplifySetCC(): recanonicalize `(X&1) != 0` (PR51312)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:3875
+          // If this is (X&1) == / != 1,   normalize it to (X&1) != / == 0.
+          // If this is (X&1)      != 0, renormalize it to (X&1)      != 0.
+          SDValue OrigOp0 = Op0;
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Does this renormalize only happen if VT doesn't match Op0.getValueType()?


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Comment at: llvm/test/CodeGen/SystemZ/int-cmp-47.ll:270
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    tmhh %r2, 256
+; CHECK-NEXT:    srlg %r0, %r2, 56
+; CHECK-NEXT:    tmll %r0, 1
----------------
 Is this a regression?


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Comment at: llvm/test/CodeGen/X86/parity-vec.ll:66
 ; CHECK-NEXT:    testb $1, %al
 ; CHECK-NEXT:    sete %al
 ; CHECK-NEXT:    retq
----------------
Is this a different issue?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D107406/new/

https://reviews.llvm.org/D107406