[PATCH] D106549: [AArch64][SVE] Combine bitcasts to predicate types with vector inserts of loads

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added inline comments.
This revision is now accepted and ready to land.


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Comment at: llvm/lib/Target/AArch64/SVEIntrinsicOpts.cpp:338
+
+  Store->replaceAllUsesWith(StorePred);
+  Store->eraseFromParent();
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Not sure why I've only just spotted this but does this do anything? Can there be any uses of a store?


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Comment at: llvm/test/CodeGen/AArch64/sve-insert-vector-to-predicate-load.ll:61-64
+  %load = load <4 x i8>, <4 x i8>* %addr, align 4
+  %insert = tail call <vscale x 2 x i8> @llvm.experimental.vector.insert.nxv2i8.v4i8(<vscale x 2 x i8> undef, <4 x i8> %load, i64 0)
+  %ret = bitcast <vscale x 2 x i8> %insert to <vscale x 16 x i1>
+  ret <vscale x 16 x i1> %ret
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Not really relevant for this patch but it occurs to me that this IR is provably bogus if we wanted to add the necessary hooks into the verifier.


Repository:
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  https://reviews.llvm.org/D106549/new/

https://reviews.llvm.org/D106549