[PATCH] D107306: [AArch64] Prefer ZIP1 over INS to lower concat_vectors.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Oh, that's unfortunate... I'll just abandon this for now, then; it's not blocking anything for me.

I see a couple ways forward here:

1. Specialize the generated code based on the target CPU.
2. Generate zip1, but add an optimization after regalloc to transform zip1 to ins if the destination is equal to one of the source registers.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107306/new/

https://reviews.llvm.org/D107306