[PATCH] D106447: [DAGCombine] DAGTypeLegalizer::GenWidenVectorLoads(): make use of dereferenceability knowledge

Jay Foad via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Aug 2 01:36:06 PDT 2021


foad added a comment.

In D106447#2917507 <https://reviews.llvm.org/D106447#2917507>, @lebedev.ri wrote:

> Rebased after D107052 <https://reviews.llvm.org/D107052> (thanks!)
> I think the AMDGPU test change looks somewhat less scary now.
> Thoughts?

I think we will still need a target hook or some other way of restricting this. In the v5i64_arg case I quoted earlier we're loading 16 dwords instead of 10. Yes the 16-dword load is legal, but that doesn't mean it's a good idea to use it. It increases register pressure (which is especially bad on GPUs) and may load from more cache lines.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106447/new/

https://reviews.llvm.org/D106447



More information about the llvm-commits mailing list