[PATCH] D107068: [DAG] DAGCombiner::visitVECTOR_SHUFFLE - recognise INSERT_SUBVECTOR patterns.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

Vector element mov is generally the same cost as zip1 on aarch64; zip1 is preferable because we can specify the destination register.

https://github.com/llvm/llvm-project/blob/56e7b6c3924d7ba8db70c38235a77ed8208795eb/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp#L10552 is supposed to ensure that only INSERT_SUBVECTOR with index 0 is legal, I think?  Maybe it broke somehow.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D107068/new/

https://reviews.llvm.org/D107068