[PATCH] D106633: [RISCV][Docs] Add description about inline asm constraint for V.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai updated this revision to Diff 363000.
HsiangKai added a comment.

After D107139 <https://reviews.llvm.org/D107139>, usr 'vr' for vector register and 'vm' for vector mask in IR.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106633/new/

https://reviews.llvm.org/D106633

Files:
  llvm/docs/LangRef.rst


Index: llvm/docs/LangRef.rst
===================================================================
--- llvm/docs/LangRef.rst
+++ llvm/docs/LangRef.rst
@@ -4767,6 +4767,8 @@
 - ``f``: A 32- or 64-bit floating-point register (requires F or D extension).
 - ``r``: A 32- or 64-bit general-purpose register (depending on the platform
   ``XLEN``).
+- ``vr``: A vector register. (requires V extension).
+- ``vm``: A vector mask register. (requires V extension).
 
 Sparc:
 


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