[PATCH] D106633: [RISCV][Docs] Add description about inline asm constraint for V.

[Kito Cheng via Phabricator via llvm-commits]

kito-cheng added inline comments.


================
Comment at: llvm/docs/LangRef.rst:4770
   ``XLEN``).
+- ``v``: A vector register. Clang uses ``vr`` for vector registers and ``vm``
+  for vector mask registers. (requires V extension).
----------------
HsiangKai wrote:
> kito-cheng wrote:
> > I thought we only support `vr` and `vm`, but `v` only is not supported?
> In LLVM IR, it still keeps to only use 'v'. The document is IR document. That's why I describe 'v' here.
> 
> In Clang, it will convert 'vr' and 'vm' to 'v' in LLVM IR.
> 
> You could see the `convertConstraint` in https://reviews.llvm.org/D98616.
Description at the begin of this chapter 
````
The constraint codes are, in general, expected to behave the same way they do in GCC. LLVM’s support is often implemented on an ‘as-needed’ basis, to support C inline asm code which was supported by GCC. A mismatch in behavior between LLVM and GCC likely indicates a bug in LLVM.
```

I would suggest remove `v`, it's impossible to implement `v` and `vr`/`vm` on GCC site.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106633/new/

https://reviews.llvm.org/D106633