[PATCH] D107088: [ARC] Add additional mov immediate instruction formats with a fix for u6 decoding

[Mark Schimmel via Phabricator via llvm-commits]

marksl added inline comments.


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Comment at: llvm/test/MC/Disassembler/ARC/alu.txt:195
 
+# CHECK: rsub.eq %r0, %r0, 31
+0xce 0x20 0xe1 0x07
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You should probably check something other than R0 to verify the field is defined correctly. R0 will just encode zeros which may not show up an error.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D107088/new/

https://reviews.llvm.org/D107088