[PATCH] D107068: [DAG] DAGCombiner::visitVECTOR_SHUFFLE - recognise INSERT_SUBVECTOR patterns.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: spatel, craig.topper, pengfei, dmgreen, t.p.northover, fhahn.
Herald added subscribers: ecnelises, hiraditya, kristof.beyls.
RKSimon requested review of this revision.
Herald added a project: LLVM.

IR typically creates INSERT_SUBVECTOR patterns as a widening of the subvector with undefs to pad to the destination size, followed by a shuffle for the actual insertion - SelectionDAGBuilder has to do something similar for shuffles when source/destination vectors are different sizes.

This combine attempts to recognize these patterns by looking for a shuffle of a subvector (from a CONCAT_VECTORS) that starts at a modulo of its size into an otherwise identity shuffle of the base vector.

This uncovered a couple of target-specific issues as we haven't often created INSERT_SUBVECTOR nodes in generic code - aarch64 could only handle insertions into the bottom of undefs (i.e. a vector widening), and x86-avx512 vXi1 insertion wasn't keeping track of undef elements in the base vector.

For the aarch64 change - I'm assuming a move is cheaper than a zip, but we can change the isel pattern if I'm wrong. If the aarch64 team prefers, we could add fixed vector handling for INSERT_SUBVECTOR to AArch64DAGToDAGISel::Select?

Fixes PR50053


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107068

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
  llvm/test/CodeGen/X86/2012-04-26-sdglue.ll
  llvm/test/CodeGen/X86/avx-intrinsics-x86-upgrade.ll
  llvm/test/CodeGen/X86/avx-vperm2x128.ll
  llvm/test/CodeGen/X86/pr34592.ll

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