[PATCH] D106272: [AArch64][SME] Introduce feature for streaming mode

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:1584-1587
+  defm BFMMLA_B_ZZZ : sve_bfloat_matmul_longvecl<0b0, "bfmlalb", int_aarch64_sve_bfmlalb>;
+  defm BFMMLA_T_ZZZ : sve_bfloat_matmul_longvecl<0b1, "bfmlalt", int_aarch64_sve_bfmlalt>;
+  defm BFMMLA_B_ZZI : sve_bfloat_matmul_longvecl_idx<0b0, "bfmlalb", int_aarch64_sve_bfmlalb_lane>;
+  defm BFMMLA_T_ZZI : sve_bfloat_matmul_longvecl_idx<0b1, "bfmlalt", int_aarch64_sve_bfmlalt_lane>;
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sdesmalen wrote:
> the BFMMLA instructions are illegal under streaming SVE mode.
> the BFMMLA instructions are illegal under streaming SVE mode.

BFMMLA is: https://developer.arm.com/documentation/ddi0602/2021-06/SVE-Instructions/BFMMLA--BFloat16-floating-point-matrix-multiply-accumulate-

but these variants aren't, e.g. https://developer.arm.com/documentation/ddi0602/2021-06/SVE-Instructions/BFMLALB--indexed---BFloat16-floating-point-multiply-add-long-to-single-precision--bottom--indexed--


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:2180
   // 2-element contiguous non-faulting loads
   defm : ldnf1<LDNF1B_D_IMM,  nxv2i64,  AArch64ldnf1_z,  nxv2i1, nxv2i8>;
   defm : ldnf1<LDNF1SB_D_IMM, nxv2i64,  AArch64ldnf1s_z, nxv2i1, nxv2i8>;
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sdesmalen wrote:
> Patterns must be similarly guarded by HasSVE. They're not valid under HasStreamingSVE because the instructions they target otherwise don't exist.
> Patterns must be similarly guarded by HasSVE. They're not valid under HasStreamingSVE because the instructions they target otherwise don't exist.

Ah good spot, I'll fix this cheers.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106272/new/

https://reviews.llvm.org/D106272