[PATCH] D106272: [AArch64][SME] Introduce feature for streaming mode

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

Some things that are missing from this patch, but which can probably be followed up in separate patches:

- A small subset of the AdvSimd instructions can be used under Streaming SVE, so we'll need something like hasNeonOrStreamingSVE as well.
- We'll need to change calls to `Subtarget->hasSVE()` in e.g. AArch64ISelLowering.cpp or AArch64TargetTransformInfo.cpp to use `Subtarget->hasSVEOrStreamingSVE()` where appropriate.



================
Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:1584-1587
+  defm BFMMLA_B_ZZZ : sve_bfloat_matmul_longvecl<0b0, "bfmlalb", int_aarch64_sve_bfmlalb>;
+  defm BFMMLA_T_ZZZ : sve_bfloat_matmul_longvecl<0b1, "bfmlalt", int_aarch64_sve_bfmlalt>;
+  defm BFMMLA_B_ZZI : sve_bfloat_matmul_longvecl_idx<0b0, "bfmlalb", int_aarch64_sve_bfmlalb_lane>;
+  defm BFMMLA_T_ZZI : sve_bfloat_matmul_longvecl_idx<0b1, "bfmlalt", int_aarch64_sve_bfmlalt_lane>;
----------------
the BFMMLA instructions are illegal under streaming SVE mode.


================
Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:2180
   // 2-element contiguous non-faulting loads
   defm : ldnf1<LDNF1B_D_IMM,  nxv2i64,  AArch64ldnf1_z,  nxv2i1, nxv2i8>;
   defm : ldnf1<LDNF1SB_D_IMM, nxv2i64,  AArch64ldnf1s_z, nxv2i1, nxv2i8>;
----------------
Patterns must be similarly guarded by HasSVE. They're not valid under HasStreamingSVE because the instructions they target otherwise don't exist.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106272/new/

https://reviews.llvm.org/D106272