[PATCH] D106651: [RISCV] Add support for vector saturating add/sub operations

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Looks like ARM also has a saturating flag but haven't implemented the defined intrinsics for it due to complexities with needing to know when the bit is accessed. See https://reviews.llvm.org/D32282


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106651/new/

https://reviews.llvm.org/D106651