[PATCH] D106273: [SVE][AArch64] Improve code generation for vector_splice for Imm > 0

[Caroline via Phabricator via llvm-commits]

CarolineConcatto marked 2 inline comments as done.
CarolineConcatto added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:245
+  template <signed Min, signed Max, signed Scale>
+  bool SelectEXTImm(SDValue N, SDValue &Imm) {
+    if (!isa<ConstantSDNode>(N))
----------------
david-arm wrote:
> Just a thought, but do we even need a `Min` here since it always seems to be `0` anyway? We could just compare directly against `0` in the if statement below.
Yes, it is possible. 
I followed the same pattern as in` bool SelectCntImm(SDValue N, SDValue &Imm) `.
But I believe there is no problem with changing it. We could add the minimum parameter again if this function is used in the future with other minimum ranges.




Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106273/new/

https://reviews.llvm.org/D106273