[PATCH] D106273: [SVE][AArch64] Improve code generation for vector_splice for Imm > 0

[Caroline via Phabricator via llvm-commits]

CarolineConcatto updated this revision to Diff 361589.
CarolineConcatto added a comment.

- Add test for unpacked types with idx != 0
- Remove Min parameter from SelectEXTImm


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106273/new/

https://reviews.llvm.org/D106273

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

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