[PATCH] D106780: [x86] Fix lowering to illegal type in LowerINSERT_VECTOR_ELT

[Xiang Zhang via Phabricator via llvm-commits]

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A bugfix for X86TargetLowering:
For INSERT_VECTOR_ELT, X86TargetLowering may try to generate illegal type, for example v2i64 in special 32-bits target.
Because this Lowering optimization is done after Type Legalization, so we can no longer convert illegal type to legal again.


https://reviews.llvm.org/D106780

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/vector_double2_insert.ll


Index: llvm/test/CodeGen/X86/vector_double2_insert.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/vector_double2_insert.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -O0 -mtriple i686-pc-win32-msvc -mcpu=skx               | FileCheck %s
+
+define void @vector_double2_insert() {
+; CHECK-LABEL: vector_double2_insert:
+; CHECK:       # %bb.0: # %wrapper_entry
+; CHECK-NEXT:    pushl %ebp
+; CHECK-NEXT:    movl %esp, %ebp
+; CHECK-NEXT:    andl $-16, %esp
+; CHECK-NEXT:    subl $32, %esp
+; CHECK-NEXT:    # implicit-def: $eax
+; CHECK-NEXT:    movl (%eax), %eax
+; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    vpxor %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    vmovapd %xmm0, (%esp)
+; CHECK-NEXT:    movl $0, 4(%esp,%eax,8)
+; CHECK-NEXT:    movl $0, (%esp,%eax,8)
+; CHECK-NEXT:    vmovapd (%esp), %xmm0
+; CHECK-NEXT:    # implicit-def: $eax
+; CHECK-NEXT:    vmovapd %xmm0, (%eax)
+wrapper_entry:
+  %explicit_2 = load i32, i32* undef, align 4
+  %0 = insertelement <2 x double> zeroinitializer, double 0.000000e+00, i32 %explicit_2
+  store <2 x double> %0, <2 x double> addrspace(1)* undef, align 16
+  unreachable
+}
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -18909,6 +18909,9 @@
 
     MVT IdxSVT = MVT::getIntegerVT(EltSizeInBits);
     MVT IdxVT = MVT::getVectorVT(IdxSVT, NumElts);
+    if (!isTypeLegal(IdxSVT) || !isTypeLegal(IdxVT))
+      return SDValue();
+
     SDValue IdxExt = DAG.getZExtOrTrunc(N2, dl, IdxSVT);
     SDValue IdxSplat = DAG.getSplatBuildVector(IdxVT, dl, IdxExt);
     SDValue EltSplat = DAG.getSplatBuildVector(VT, dl, N1);


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