[PATCH] D105130: [RISCV] Enable interleaved access vectorization

[Luke via Phabricator via llvm-commits]

luke957 added inline comments.


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Comment at: llvm/test/Transforms/LoopVectorize/RISCV/interleaved-accesses.ll:4
+; RUN:   -loop-vectorize -instcombine -force-vector-width=4 \
+; RUN:   -force-vector-interleave=1 -enable-interleaved-mem-accesses=true \
+; RUN:   -runtime-memory-check-threshold=24 < %s | FileCheck %s
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craig.topper wrote:
> Is `-enable-interleaved-mem-accesses=true` needed if TTI enableInterleavedAccessVectorization() returns true
Yes, `-enable-interleaved-mem-accesses=true` is not needed any longer.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105130/new/

https://reviews.llvm.org/D105130