[PATCH] D105130: [RISCV] Enable interleaved access vectorization

[Luke via Phabricator via llvm-commits]

luke957 added a comment.

In D105130#2847617 <https://reviews.llvm.org/D105130#2847617>, @craig.topper wrote:

> Please upload patches with full context using -U999999 has documented here https://releases.llvm.org/11.0.0/docs/Phabricator.html#requesting-a-review-via-the-web-interface
>
> Do you plan to map these to segment load/store instructions in the future?

Yeah, segment load/store instructions are naturally suitable for mapping these. Do we need to create a new RISCVISD?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D105130/new/

https://reviews.llvm.org/D105130