[PATCH] D106651: [RISCV] Add support for vector saturating add/sub operations

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jul 23 10:13:05 PDT 2021

Previous message: [PATCH] D106651: [RISCV] Add support for vector saturating add/sub operations
Next message: [PATCH] D106652: [SelectionDAG] Support scalable splats in U(ADD|SUB)SAT combines
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

craig.topper added a comment.

These instructions can set the vxsat bit. How does that interact with other code around that might want to read the vxsat bit?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106651/new/

https://reviews.llvm.org/D106651

Previous message: [PATCH] D106651: [RISCV] Add support for vector saturating add/sub operations
Next message: [PATCH] D106652: [SelectionDAG] Support scalable splats in U(ADD|SUB)SAT combines
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list