[PATCH] D106651: [RISCV] Add support for vector saturating add/sub operations

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck created this revision.
frasercrmck added reviewers: craig.topper, rogfer01, evandro, HsiangKai, khchen.
Herald added subscribers: vkmr, luismarques, apazos, sameer.abuasal, steven.zhang, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
frasercrmck requested review of this revision.
Herald added subscribers: llvm-commits, MaskRay.
Herald added a project: LLVM.

This patch adds support for lowering the saturating vector add/sub
intrinsics to RVV instructions, for both fixed-length and
scalable-vector forms alike.

Note that some of the DAG combines are still not triggering for the
scalable-vector tests. These require a bit more work in the DAGCombiner
itself.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106651

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/combine-sats.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll
  llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll

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