[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: clang/include/clang/Basic/riscv_vector.td:680
       foreach type = TypeList in {
-        foreach eew_list = EEWList in {
+        foreach eew_list = Xlen32EEWList in {
           defvar eew = eew_list[0];
----------------
There is no need to define `Xlen32EEWList`. You could use `EEWList[0-2]` for the purpose.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106518/new/

https://reviews.llvm.org/D106518