[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added inline comments.


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Comment at: clang/include/clang/Basic/riscv_vector.td:555
 
+defvar Xlen32EEWList = [["8", "(Log2EEW:3)"],
+                        ["16", "(Log2EEW:4)"],
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frasercrmck wrote:
> jrtc27 wrote:
> > Ignoring whether the change is actually correct, this should be capitalised as XLen32EEWList, but really this should actually be RV32 not XLen32 as that's not a term we use.
> While we're here I'm wondering whether a top-level `Xlen32EEWList`/`RV32EEWList` is conveying the wrong thing. It's only the loads and stores that have a different EEW list on RV32, isn't it?
Yes, only for index load/store, we should add the macro to the generated header to make `EEW=64` just available on RV64.


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  https://reviews.llvm.org/D106518/new/

https://reviews.llvm.org/D106518