[PATCH] D106561: [AArch64] Optimise min/max lowering in ISel

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll:90
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:   mov     x8, v0.d[1]
-; CHECK-NEXT:   fmov    x9, d0
-; CHECK-NEXT:   cmp     x9, x8
-; CHECK-NEXT:   csel    x0, x9, x8, hi
-; CHECK-NEXT:   ret
+; CHECK-NEXT:    ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT:    cmhi d2, d0, d1
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david-arm wrote:
> Hi @Rin, at first glance this code looks like it might be worse than before? I realise the instruction count is the same, but I wonder if the cost of 'ext' might be higher?
Why would the cost of an ext be higher?


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https://reviews.llvm.org/D106561