[PATCH] D106561: [AArch64] Optimise min/max lowering in ISel

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:4781
   case ISD::SMIN:
-    return LowerToPredicatedOp(Op, DAG, AArch64ISD::SMIN_PRED,
-                               /*OverrideNEON=*/true);
+    return LowerMinMax(Op, DAG);
   case ISD::UMIN:
----------------
These can use fallthroughs to the next case, if they all call LowerMinMax in the same way.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7107
+
+  if ((VT != MVT::v1i64 && VT != MVT::v2i64) ||
+      useSVEForFixedLengthVectorVT(VT, /*OverrideNEON=*/true)) {
----------------
Is this VT check needed?


================
Comment at: llvm/test/Analysis/CostModel/AArch64/min-max.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
 ; RUN: opt < %s -mtriple=aarch64--linux-gnu -cost-model -analyze | FileCheck %s --check-prefix=COST
----------------
I was updating this file the other day. I think if you rebase the changes may disappear.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D106561/new/

https://reviews.llvm.org/D106561