[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

[Jianjian Guan via Phabricator via llvm-commits]

jacquesguan added a comment.

In D106518#2895445 <https://reviews.llvm.org/D106518#2895445>, @craig.topper wrote:

> Why do they need to be disabled? Doesn’t the spec define them to truncate?

In the 1.0-rc1, 18.2: The V extension supports all vector load and store instructions (Section Vector Loads and Stores), except the V extension does not support EEW=64 for index values when XLEN=32.

I think this means that all index instruction with eew=64 is only supported in RV64.


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https://reviews.llvm.org/D106518