[PATCH] D106518: [RISCV] Disable EEW=64 for index values when XLEN=32.

Wed Jul 21 20:58:02 PDT 2021

jrtc27 added inline comments.

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Comment at: clang/include/clang/Basic/riscv_vector.td:555

+defvar Xlen32EEWList = [["8", "(Log2EEW:3)"],
+                        ["16", "(Log2EEW:4)"],
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Ignoring whether the change is actually correct, this should be capitalised as XLen32EEWList, but really this should actually be RV32 not XLen32 as that's not a term we use.

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Comment at: clang/include/clang/Basic/riscv_vector.td:693
+        let Name = op # eew64 # "_v", IRName = op, IRNameMask = op # "_mask",
+            RequiredExtensions = ["Xlen64"] in {
+            def: RVVBuiltin<"v", "vPCe" # eew64_type # "Uv", type>;
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Xlen64 is not an extension. Nor is RV64I, even, it is a base ISA, but that would at least be somewhat defensible. In fact, Xlen64 would be parsed as a valid non-standard extension called "Xlen" with major version 64 and minor version 0, just like any other Xfoo.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106518/new/

https://reviews.llvm.org/D106518