[llvm] 9e5c5af - [RISCV] Optimize multiplication in the zba extension with SH*ADD
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 21 19:29:06 PDT 2021
Author: Ben Shi
Date: 2021-07-22T10:28:41+08:00
New Revision: 9e5c5afc7ee24ace168418138c99dcede357cd50
URL: https://github.com/llvm/llvm-project/commit/9e5c5afc7ee24ace168418138c99dcede357cd50
DIFF: https://github.com/llvm/llvm-project/commit/9e5c5afc7ee24ace168418138c99dcede357cd50.diff
LOG: [RISCV] Optimize multiplication in the zba extension with SH*ADD
This patch make the following optimization.
(mul x, 3 * power_of_2) -> (SLLI (SH1ADD x, x), bits)
(mul x, 5 * power_of_2) -> (SLLI (SH2ADD x, x), bits)
(mul x, 9 * power_of_2) -> (SLLI (SH3ADD x, x), bits)
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D105796
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
llvm/test/CodeGen/RISCV/rv32zba.ll
llvm/test/CodeGen/RISCV/rv64zba.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
index 7d8d053cc584b..7359e567a58dd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td
@@ -99,7 +99,7 @@ def BSETINVTwoBitsMask : PatLeaf<(imm), [{
return countPopulation(N->getZExtValue()) == 2;
}]>;
-def BSETINVTwoBitsMaskLow : SDNodeXForm<imm, [{
+def TrailingZerosXForm : SDNodeXForm<imm, [{
uint64_t I = N->getZExtValue();
return CurDAG->getTargetConstant(countTrailingZeros(I), SDLoc(N),
N->getValueType(0));
@@ -171,6 +171,21 @@ def BCLRIANDIMaskLow : SDNodeXForm<imm, [{
SDLoc(N), N->getValueType(0));
}]>;
+def C3LeftShift : PatLeaf<(imm), [{
+ uint64_t C = N->getZExtValue();
+ return C > 3 && ((C % 3) == 0) && isPowerOf2_64(C / 3);
+}]>;
+
+def C5LeftShift : PatLeaf<(imm), [{
+ uint64_t C = N->getZExtValue();
+ return C > 5 && ((C % 5) == 0) && isPowerOf2_64(C / 5);
+}]>;
+
+def C9LeftShift : PatLeaf<(imm), [{
+ uint64_t C = N->getZExtValue();
+ return C > 9 && ((C % 9) == 0) && isPowerOf2_64(C / 9);
+}]>;
+
//===----------------------------------------------------------------------===//
// Instruction class templates
//===----------------------------------------------------------------------===//
@@ -809,10 +824,10 @@ def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1)),
(BEXTI GPR:$rs1, uimmlog2xlen:$shamt)>;
def : Pat<(or GPR:$r, BSETINVTwoBitsMask:$i),
- (BSETI (BSETI GPR:$r, (BSETINVTwoBitsMaskLow BSETINVTwoBitsMask:$i)),
+ (BSETI (BSETI GPR:$r, (TrailingZerosXForm BSETINVTwoBitsMask:$i)),
(BSETINVTwoBitsMaskHigh BSETINVTwoBitsMask:$i))>;
def : Pat<(xor GPR:$r, BSETINVTwoBitsMask:$i),
- (BINVI (BINVI GPR:$r, (BSETINVTwoBitsMaskLow BSETINVTwoBitsMask:$i)),
+ (BINVI (BINVI GPR:$r, (TrailingZerosXForm BSETINVTwoBitsMask:$i)),
(BSETINVTwoBitsMaskHigh BSETINVTwoBitsMask:$i))>;
def : Pat<(or GPR:$r, BSETINVORIMask:$i),
(BSETI (ORI GPR:$r, (BSETINVORIMaskLow BSETINVORIMask:$i)),
@@ -995,6 +1010,16 @@ def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 40)), GPR:$rs2),
(SH3ADD (SH2ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 72)), GPR:$rs2),
(SH3ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
+
+def : Pat<(mul GPR:$r, C3LeftShift:$i),
+ (SLLI (SH1ADD GPR:$r, GPR:$r),
+ (TrailingZerosXForm C3LeftShift:$i))>;
+def : Pat<(mul GPR:$r, C5LeftShift:$i),
+ (SLLI (SH2ADD GPR:$r, GPR:$r),
+ (TrailingZerosXForm C5LeftShift:$i))>;
+def : Pat<(mul GPR:$r, C9LeftShift:$i),
+ (SLLI (SH3ADD GPR:$r, GPR:$r),
+ (TrailingZerosXForm C9LeftShift:$i))>;
} // Predicates = [HasStdExtZba]
let Predicates = [HasStdExtZba, IsRV64] in {
diff --git a/llvm/test/CodeGen/RISCV/rv32zba.ll b/llvm/test/CodeGen/RISCV/rv32zba.ll
index 337ae520d8a05..7b2be9474d067 100644
--- a/llvm/test/CodeGen/RISCV/rv32zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zba.ll
@@ -306,14 +306,14 @@ define i32 @mul96(i32 %a) {
;
; RV32IB-LABEL: mul96:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: addi a1, zero, 96
-; RV32IB-NEXT: mul a0, a0, a1
+; RV32IB-NEXT: sh1add a0, a0, a0
+; RV32IB-NEXT: slli a0, a0, 5
; RV32IB-NEXT: ret
;
; RV32IBA-LABEL: mul96:
; RV32IBA: # %bb.0:
-; RV32IBA-NEXT: addi a1, zero, 96
-; RV32IBA-NEXT: mul a0, a0, a1
+; RV32IBA-NEXT: sh1add a0, a0, a0
+; RV32IBA-NEXT: slli a0, a0, 5
; RV32IBA-NEXT: ret
%c = mul i32 %a, 96
ret i32 %c
@@ -328,14 +328,14 @@ define i32 @mul160(i32 %a) {
;
; RV32IB-LABEL: mul160:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: addi a1, zero, 160
-; RV32IB-NEXT: mul a0, a0, a1
+; RV32IB-NEXT: sh2add a0, a0, a0
+; RV32IB-NEXT: slli a0, a0, 5
; RV32IB-NEXT: ret
;
; RV32IBA-LABEL: mul160:
; RV32IBA: # %bb.0:
-; RV32IBA-NEXT: addi a1, zero, 160
-; RV32IBA-NEXT: mul a0, a0, a1
+; RV32IBA-NEXT: sh2add a0, a0, a0
+; RV32IBA-NEXT: slli a0, a0, 5
; RV32IBA-NEXT: ret
%c = mul i32 %a, 160
ret i32 %c
@@ -350,14 +350,14 @@ define i32 @mul288(i32 %a) {
;
; RV32IB-LABEL: mul288:
; RV32IB: # %bb.0:
-; RV32IB-NEXT: addi a1, zero, 288
-; RV32IB-NEXT: mul a0, a0, a1
+; RV32IB-NEXT: sh3add a0, a0, a0
+; RV32IB-NEXT: slli a0, a0, 5
; RV32IB-NEXT: ret
;
; RV32IBA-LABEL: mul288:
; RV32IBA: # %bb.0:
-; RV32IBA-NEXT: addi a1, zero, 288
-; RV32IBA-NEXT: mul a0, a0, a1
+; RV32IBA-NEXT: sh3add a0, a0, a0
+; RV32IBA-NEXT: slli a0, a0, 5
; RV32IBA-NEXT: ret
%c = mul i32 %a, 288
ret i32 %c
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
index c47619404640c..51691709eb680 100644
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -596,14 +596,14 @@ define i64 @mul96(i64 %a) {
;
; RV64IB-LABEL: mul96:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: addi a1, zero, 96
-; RV64IB-NEXT: mul a0, a0, a1
+; RV64IB-NEXT: sh1add a0, a0, a0
+; RV64IB-NEXT: slli a0, a0, 5
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: mul96:
; RV64IBA: # %bb.0:
-; RV64IBA-NEXT: addi a1, zero, 96
-; RV64IBA-NEXT: mul a0, a0, a1
+; RV64IBA-NEXT: sh1add a0, a0, a0
+; RV64IBA-NEXT: slli a0, a0, 5
; RV64IBA-NEXT: ret
%c = mul i64 %a, 96
ret i64 %c
@@ -618,14 +618,14 @@ define i64 @mul160(i64 %a) {
;
; RV64IB-LABEL: mul160:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: addi a1, zero, 160
-; RV64IB-NEXT: mul a0, a0, a1
+; RV64IB-NEXT: sh2add a0, a0, a0
+; RV64IB-NEXT: slli a0, a0, 5
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: mul160:
; RV64IBA: # %bb.0:
-; RV64IBA-NEXT: addi a1, zero, 160
-; RV64IBA-NEXT: mul a0, a0, a1
+; RV64IBA-NEXT: sh2add a0, a0, a0
+; RV64IBA-NEXT: slli a0, a0, 5
; RV64IBA-NEXT: ret
%c = mul i64 %a, 160
ret i64 %c
@@ -640,14 +640,14 @@ define i64 @mul288(i64 %a) {
;
; RV64IB-LABEL: mul288:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: addi a1, zero, 288
-; RV64IB-NEXT: mul a0, a0, a1
+; RV64IB-NEXT: sh3add a0, a0, a0
+; RV64IB-NEXT: slli a0, a0, 5
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: mul288:
; RV64IBA: # %bb.0:
-; RV64IBA-NEXT: addi a1, zero, 288
-; RV64IBA-NEXT: mul a0, a0, a1
+; RV64IBA-NEXT: sh3add a0, a0, a0
+; RV64IBA-NEXT: slli a0, a0, 5
; RV64IBA-NEXT: ret
%c = mul i64 %a, 288
ret i64 %c
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