[PATCH] D106471: [DAGCombiner][RISCV][AMDGPU] Call SimplifyDemandedBits at the end of visitMULHU to enable known bits contant folding.

Wed Jul 21 11:57:07 PDT 2021

craig.topper added inline comments.

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Comment at: llvm/test/CodeGen/AMDGPU/sdiv64.ll:1425
-; GCN-NEXT:    v_mul_hi_u32 v6, 24, v4
-; GCN-NEXT:    v_mul_hi_u32 v4, 0, v4
 ; GCN-NEXT:    v_add_i32_e32 v3, vcc, v3, v5
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This also points to a failure to canonicalize constants to the RHS so the isNullValue check in visitMULHU would work. I tried to add the canonicalization without this patch, but ended up with a verifier failure on some AMDGPU tests.

It appears the simplification introduced in this patch catches something even earlier and produces simpler code that doesn't hit the verifier error.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106471/new/

https://reviews.llvm.org/D106471