[PATCH] D106471: [DAGCombiner][RISCV][AMDGPU] Call SimplifyDemandedBits at the end of visitMULHU to enable known bits contant folding.

[Craig Topper via Phabricator via llvm-commits]

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We don't have real demanded bits support for MULHU, but we can
still use the known bits based constant folding support at the end
of SimplifyDemandedBits to simplify a MULHU. This helps with cases
where we know the LHS and RHS have enough leading zeros so that
the high multiply result is always 0.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106471

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/AMDGPU/sdiv64.ll
  llvm/test/CodeGen/AMDGPU/srem64.ll
  llvm/test/CodeGen/AMDGPU/udiv64.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
  llvm/test/CodeGen/RISCV/rvv/stepvector.ll

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