[PATCH] D106273: [WIP] Improve code generation for vector_splice for Imm > 0

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a comment.

Is this patch still work-in-progress, or is it ready to review? (it looks like the latter)



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7431
+  if ((!Op.getConstantOperandAPInt(2).isNegative() &&
+       Ty.getVectorMinNumElements() > Op.getConstantOperandVal(2)) ||
+      Op.getConstantOperandAPInt(2) == -1)
----------------
Why is this condition relevant?


================
Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:2402
+
+  // Splice with lane bigger or equalt to 0
+  def : Pat<(nxv16i8 (vector_splice (nxv16i8 ZPR:$Z1), (nxv16i8 ZPR:$Z2), (i64 (sve_ext_imm_0_15 i32:$index)))),
----------------
nit: s/equalt/equal/


================
Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:2410
+  def : Pat<(nxv2i64 (vector_splice (nxv2i64 ZPR:$Z1), (nxv2i64 ZPR:$Z2), (i64 (sve_ext_imm_0_1 i32:$index)))),
+          (EXT_ZZI  ZPR:$Z1, ZPR:$Z2, sve_ext_imm_0_1:$index)>;
   }
----------------
nit: indentation


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106273/new/

https://reviews.llvm.org/D106273