[PATCH] D106273: [WIP] Improve code generation for vector_splice for Imm > 0

[Caroline via Phabricator via llvm-commits]

CarolineConcatto created this revision.
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This patch implements vector_splice in tablegen for all cases when the
Immediate is positive and lower than the known minimum value of
a scalable vector.
Vector_splice can be implemented using SVE instruction EXT.
For instance :

  @llvm.experimental.vector.splice(Vector_1, Vector_2, Imm)
  @llvm.experimental.vector.splice(<A,B,C,D>, <E,F,G,H>, 1) ==> <B, C, D, E>
      EXT  Vector_1, Vector_2, Imm              // Vector_1 = B, C, D + Vector_2 = E

Depends on D105633 <https://reviews.llvm.org/D105633>


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106273

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll

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