[llvm] d3738a0 - [RISCV][test] Add tests for mul optimization in the zba extension with SH*ADD
Ben Shi via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 20 19:17:08 PDT 2021
Author: Ben Shi
Date: 2021-07-21T10:16:56+08:00
New Revision: d3738a09fb2587f584cec5faefda1f37743524a5
URL: https://github.com/llvm/llvm-project/commit/d3738a09fb2587f584cec5faefda1f37743524a5
DIFF: https://github.com/llvm/llvm-project/commit/d3738a09fb2587f584cec5faefda1f37743524a5.diff
LOG: [RISCV][test] Add tests for mul optimization in the zba extension with SH*ADD
These tests will show the following optimization by future patches.
(mul x, 11) -> (SH1ADD (SH2ADD x, x), x)
(mul x, 19) -> (SH1ADD (SH3ADD x, x), x)
(mul x, 13) -> (SH2ADD (SH1ADD x, x), x)
(mul x, 21) -> (SH2ADD (SH2ADD x, x), x)
(mul x, 37) -> (SH2ADD (SH3ADD x, x), x)
(mul x, 25) -> (SH3ADD (SH1ADD x, x), x)
(mul x, 41) -> (SH3ADD (SH2ADD x, x), x)
(mul x, 73) -> (SH3ADD (SH3ADD x, x), x)
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D106031
Added:
Modified:
llvm/test/CodeGen/RISCV/rv32zba.ll
llvm/test/CodeGen/RISCV/rv64zba.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rv32zba.ll b/llvm/test/CodeGen/RISCV/rv32zba.ll
index e7b8069862d0a..337ae520d8a05 100644
--- a/llvm/test/CodeGen/RISCV/rv32zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zba.ll
@@ -428,3 +428,179 @@ define i32 @mul264(i32 %a) {
%c = mul i32 %a, 264
ret i32 %c
}
+
+define i32 @mul11(i32 %a) {
+; RV32I-LABEL: mul11:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi a1, zero, 11
+; RV32I-NEXT: mul a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: mul11:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: addi a1, zero, 11
+; RV32IB-NEXT: mul a0, a0, a1
+; RV32IB-NEXT: ret
+;
+; RV32IBA-LABEL: mul11:
+; RV32IBA: # %bb.0:
+; RV32IBA-NEXT: addi a1, zero, 11
+; RV32IBA-NEXT: mul a0, a0, a1
+; RV32IBA-NEXT: ret
+ %c = mul i32 %a, 11
+ ret i32 %c
+}
+
+define i32 @mul19(i32 %a) {
+; RV32I-LABEL: mul19:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi a1, zero, 19
+; RV32I-NEXT: mul a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: mul19:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: addi a1, zero, 19
+; RV32IB-NEXT: mul a0, a0, a1
+; RV32IB-NEXT: ret
+;
+; RV32IBA-LABEL: mul19:
+; RV32IBA: # %bb.0:
+; RV32IBA-NEXT: addi a1, zero, 19
+; RV32IBA-NEXT: mul a0, a0, a1
+; RV32IBA-NEXT: ret
+ %c = mul i32 %a, 19
+ ret i32 %c
+}
+
+define i32 @mul13(i32 %a) {
+; RV32I-LABEL: mul13:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi a1, zero, 13
+; RV32I-NEXT: mul a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: mul13:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: addi a1, zero, 13
+; RV32IB-NEXT: mul a0, a0, a1
+; RV32IB-NEXT: ret
+;
+; RV32IBA-LABEL: mul13:
+; RV32IBA: # %bb.0:
+; RV32IBA-NEXT: addi a1, zero, 13
+; RV32IBA-NEXT: mul a0, a0, a1
+; RV32IBA-NEXT: ret
+ %c = mul i32 %a, 13
+ ret i32 %c
+}
+
+define i32 @mul21(i32 %a) {
+; RV32I-LABEL: mul21:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi a1, zero, 21
+; RV32I-NEXT: mul a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: mul21:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: addi a1, zero, 21
+; RV32IB-NEXT: mul a0, a0, a1
+; RV32IB-NEXT: ret
+;
+; RV32IBA-LABEL: mul21:
+; RV32IBA: # %bb.0:
+; RV32IBA-NEXT: addi a1, zero, 21
+; RV32IBA-NEXT: mul a0, a0, a1
+; RV32IBA-NEXT: ret
+ %c = mul i32 %a, 21
+ ret i32 %c
+}
+
+define i32 @mul37(i32 %a) {
+; RV32I-LABEL: mul37:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi a1, zero, 37
+; RV32I-NEXT: mul a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: mul37:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: addi a1, zero, 37
+; RV32IB-NEXT: mul a0, a0, a1
+; RV32IB-NEXT: ret
+;
+; RV32IBA-LABEL: mul37:
+; RV32IBA: # %bb.0:
+; RV32IBA-NEXT: addi a1, zero, 37
+; RV32IBA-NEXT: mul a0, a0, a1
+; RV32IBA-NEXT: ret
+ %c = mul i32 %a, 37
+ ret i32 %c
+}
+
+define i32 @mul25(i32 %a) {
+; RV32I-LABEL: mul25:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi a1, zero, 25
+; RV32I-NEXT: mul a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: mul25:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: addi a1, zero, 25
+; RV32IB-NEXT: mul a0, a0, a1
+; RV32IB-NEXT: ret
+;
+; RV32IBA-LABEL: mul25:
+; RV32IBA: # %bb.0:
+; RV32IBA-NEXT: addi a1, zero, 25
+; RV32IBA-NEXT: mul a0, a0, a1
+; RV32IBA-NEXT: ret
+ %c = mul i32 %a, 25
+ ret i32 %c
+}
+
+define i32 @mul41(i32 %a) {
+; RV32I-LABEL: mul41:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi a1, zero, 41
+; RV32I-NEXT: mul a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: mul41:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: addi a1, zero, 41
+; RV32IB-NEXT: mul a0, a0, a1
+; RV32IB-NEXT: ret
+;
+; RV32IBA-LABEL: mul41:
+; RV32IBA: # %bb.0:
+; RV32IBA-NEXT: addi a1, zero, 41
+; RV32IBA-NEXT: mul a0, a0, a1
+; RV32IBA-NEXT: ret
+ %c = mul i32 %a, 41
+ ret i32 %c
+}
+
+define i32 @mul73(i32 %a) {
+; RV32I-LABEL: mul73:
+; RV32I: # %bb.0:
+; RV32I-NEXT: addi a1, zero, 73
+; RV32I-NEXT: mul a0, a0, a1
+; RV32I-NEXT: ret
+;
+; RV32IB-LABEL: mul73:
+; RV32IB: # %bb.0:
+; RV32IB-NEXT: addi a1, zero, 73
+; RV32IB-NEXT: mul a0, a0, a1
+; RV32IB-NEXT: ret
+;
+; RV32IBA-LABEL: mul73:
+; RV32IBA: # %bb.0:
+; RV32IBA-NEXT: addi a1, zero, 73
+; RV32IBA-NEXT: mul a0, a0, a1
+; RV32IBA-NEXT: ret
+ %c = mul i32 %a, 73
+ ret i32 %c
+}
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
index f47f6b3bc156c..c47619404640c 100644
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -933,3 +933,179 @@ define i64 @imm_zextw2() nounwind {
; RV64IBA-NEXT: ret
ret i64 2863311530 ; 0xAAAAAAAA
}
+
+define i64 @mul11(i64 %a) {
+; RV64I-LABEL: mul11:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, 11
+; RV64I-NEXT: mul a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: mul11:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: addi a1, zero, 11
+; RV64IB-NEXT: mul a0, a0, a1
+; RV64IB-NEXT: ret
+;
+; RV64IBA-LABEL: mul11:
+; RV64IBA: # %bb.0:
+; RV64IBA-NEXT: addi a1, zero, 11
+; RV64IBA-NEXT: mul a0, a0, a1
+; RV64IBA-NEXT: ret
+ %c = mul i64 %a, 11
+ ret i64 %c
+}
+
+define i64 @mul19(i64 %a) {
+; RV64I-LABEL: mul19:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, 19
+; RV64I-NEXT: mul a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: mul19:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: addi a1, zero, 19
+; RV64IB-NEXT: mul a0, a0, a1
+; RV64IB-NEXT: ret
+;
+; RV64IBA-LABEL: mul19:
+; RV64IBA: # %bb.0:
+; RV64IBA-NEXT: addi a1, zero, 19
+; RV64IBA-NEXT: mul a0, a0, a1
+; RV64IBA-NEXT: ret
+ %c = mul i64 %a, 19
+ ret i64 %c
+}
+
+define i64 @mul13(i64 %a) {
+; RV64I-LABEL: mul13:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, 13
+; RV64I-NEXT: mul a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: mul13:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: addi a1, zero, 13
+; RV64IB-NEXT: mul a0, a0, a1
+; RV64IB-NEXT: ret
+;
+; RV64IBA-LABEL: mul13:
+; RV64IBA: # %bb.0:
+; RV64IBA-NEXT: addi a1, zero, 13
+; RV64IBA-NEXT: mul a0, a0, a1
+; RV64IBA-NEXT: ret
+ %c = mul i64 %a, 13
+ ret i64 %c
+}
+
+define i64 @mul21(i64 %a) {
+; RV64I-LABEL: mul21:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, 21
+; RV64I-NEXT: mul a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: mul21:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: addi a1, zero, 21
+; RV64IB-NEXT: mul a0, a0, a1
+; RV64IB-NEXT: ret
+;
+; RV64IBA-LABEL: mul21:
+; RV64IBA: # %bb.0:
+; RV64IBA-NEXT: addi a1, zero, 21
+; RV64IBA-NEXT: mul a0, a0, a1
+; RV64IBA-NEXT: ret
+ %c = mul i64 %a, 21
+ ret i64 %c
+}
+
+define i64 @mul37(i64 %a) {
+; RV64I-LABEL: mul37:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, 37
+; RV64I-NEXT: mul a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: mul37:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: addi a1, zero, 37
+; RV64IB-NEXT: mul a0, a0, a1
+; RV64IB-NEXT: ret
+;
+; RV64IBA-LABEL: mul37:
+; RV64IBA: # %bb.0:
+; RV64IBA-NEXT: addi a1, zero, 37
+; RV64IBA-NEXT: mul a0, a0, a1
+; RV64IBA-NEXT: ret
+ %c = mul i64 %a, 37
+ ret i64 %c
+}
+
+define i64 @mul25(i64 %a) {
+; RV64I-LABEL: mul25:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, 25
+; RV64I-NEXT: mul a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: mul25:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: addi a1, zero, 25
+; RV64IB-NEXT: mul a0, a0, a1
+; RV64IB-NEXT: ret
+;
+; RV64IBA-LABEL: mul25:
+; RV64IBA: # %bb.0:
+; RV64IBA-NEXT: addi a1, zero, 25
+; RV64IBA-NEXT: mul a0, a0, a1
+; RV64IBA-NEXT: ret
+ %c = mul i64 %a, 25
+ ret i64 %c
+}
+
+define i64 @mul41(i64 %a) {
+; RV64I-LABEL: mul41:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, 41
+; RV64I-NEXT: mul a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: mul41:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: addi a1, zero, 41
+; RV64IB-NEXT: mul a0, a0, a1
+; RV64IB-NEXT: ret
+;
+; RV64IBA-LABEL: mul41:
+; RV64IBA: # %bb.0:
+; RV64IBA-NEXT: addi a1, zero, 41
+; RV64IBA-NEXT: mul a0, a0, a1
+; RV64IBA-NEXT: ret
+ %c = mul i64 %a, 41
+ ret i64 %c
+}
+
+define i64 @mul73(i64 %a) {
+; RV64I-LABEL: mul73:
+; RV64I: # %bb.0:
+; RV64I-NEXT: addi a1, zero, 73
+; RV64I-NEXT: mul a0, a0, a1
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: mul73:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: addi a1, zero, 73
+; RV64IB-NEXT: mul a0, a0, a1
+; RV64IB-NEXT: ret
+;
+; RV64IBA-LABEL: mul73:
+; RV64IBA: # %bb.0:
+; RV64IBA-NEXT: addi a1, zero, 73
+; RV64IBA-NEXT: mul a0, a0, a1
+; RV64IBA-NEXT: ret
+ %c = mul i64 %a, 73
+ ret i64 %c
+}
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