[PATCH] D106286: [RISCV] Add a test showing an incorrect vsetvli insertion

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck updated this revision to Diff 360071.
frasercrmck added a comment.

- reduce the test correctly


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106286/new/

https://reviews.llvm.org/D106286

Files:
  llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll


Index: llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 | FileCheck %s
+
+; This test checks a regression in the vsetvli insertion pass. There is an
+; illegal attempt to preserve VL in the second vsetvli with ratio e32/m1, when
+; the last update of VL was the vsetvli with e64/m4.
+
+define i32 @foo(<4 x i32> %a, <vscale x 4 x i64> %x, <vscale x 4 x i64>* %y) {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; CHECK-NEXT:    vadd.vv v28, v12, v12
+; CHECK-NEXT:    vs4r.v v28, (a0)
+; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmv.x.s a0, v8
+; CHECK-NEXT:    ret
+  %index = add <vscale x 4 x i64> %x, %x
+  store <vscale x 4 x i64> %index, <vscale x 4 x i64>* %y
+  %elt = extractelement <4 x i32> %a, i64 0
+  ret i32 %elt
+}


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