[llvm] 30fa074 - AArch64/GlobalISel: Preserve memory types
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 19 17:45:54 PDT 2021
Author: Matt Arsenault
Date: 2021-07-19T20:21:05-04:00
New Revision: 30fa074c0a6e38bc605cab892f6a0474e7e6499f
URL: https://github.com/llvm/llvm-project/commit/30fa074c0a6e38bc605cab892f6a0474e7e6499f
DIFF: https://github.com/llvm/llvm-project/commit/30fa074c0a6e38bc605cab892f6a0474e7e6499f.diff
LOG: AArch64/GlobalISel: Preserve memory types
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
index 0f7542962691..81149ad2d8b8 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
@@ -146,8 +146,12 @@ struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
return AddrReg.getReg(0);
}
- LLT getStackValueStoreType(const DataLayout &, const CCValAssign &VA,
+ LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA,
ISD::ArgFlagsTy Flags) const override {
+ // For pointers, we just need to fixup the integer types reported in the
+ // CCValAssign.
+ if (Flags.isPointer())
+ return CallLowering::ValueHandler::getStackValueStoreType(DL, VA, Flags);
return getStackValueStoreTypeHack(VA);
}
@@ -167,6 +171,12 @@ struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
// Fixup the types for the DAG compatibility hack.
if (VA.getValVT() == MVT::i8 || VA.getValVT() == MVT::i16)
std::swap(ValTy, LocTy);
+ else {
+ // The calling code knows if this is a pointer or not, we're only touching
+ // the LocTy for the i8/i16 hack.
+ assert(LocTy.getSizeInBits() == MemTy.getSizeInBits());
+ LocTy = MemTy;
+ }
auto MMO = MF.getMachineMemOperand(
MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, LocTy,
@@ -252,8 +262,10 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
/// we invert the interpretation of ValVT and LocVT in certain cases. This is
/// for compatability with the DAG call lowering implementation, which we're
/// currently building on top of.
- LLT getStackValueStoreType(const DataLayout &, const CCValAssign &VA,
+ LLT getStackValueStoreType(const DataLayout &DL, const CCValAssign &VA,
ISD::ArgFlagsTy Flags) const override {
+ if (Flags.isPointer())
+ return CallLowering::ValueHandler::getStackValueStoreType(DL, VA, Flags);
return getStackValueStoreTypeHack(VA);
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 940a41e84ab4..d37be5ecf46f 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -967,6 +967,8 @@ bool AArch64LegalizerInfo::legalizeShlAshrLshr(
return true;
}
+// FIXME: This should be removed and replaced with the generic bitcast legalize
+// action.
bool AArch64LegalizerInfo::legalizeLoadStore(
MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &MIRBuilder,
GISelChangeObserver &Observer) const {
@@ -993,6 +995,8 @@ bool AArch64LegalizerInfo::legalizeLoadStore(
unsigned PtrSize = ValTy.getElementType().getSizeInBits();
const LLT NewTy = LLT::vector(ValTy.getElementCount(), PtrSize);
auto &MMO = **MI.memoperands_begin();
+ MMO.setType(NewTy);
+
if (MI.getOpcode() == TargetOpcode::G_STORE) {
auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg);
MIRBuilder.buildStore(Bitcast.getReg(0), MI.getOperand(1), MMO);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
index f05e3be2524b..6f422142a569 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/call-translator.ll
@@ -217,7 +217,7 @@ define zeroext i8 @test_abi_zext_ret(i8* %addr) {
; CHECK: [[RHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
; CHECK: [[RHS:%[0-9]+]]:_(s64) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load (s64) from %fixed-stack.[[STACK8]])
; CHECK: [[ADDR_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK16]]
-; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_LOAD [[ADDR_ADDR]](p0) :: (invariant load (s64) from %fixed-stack.[[STACK16]], align 16)
+; CHECK: [[ADDR:%[0-9]+]]:_(p0) = G_LOAD [[ADDR_ADDR]](p0) :: (invariant load (p0) from %fixed-stack.[[STACK16]], align 16)
; CHECK: [[SUM:%[0-9]+]]:_(s64) = G_ADD [[LHS]], [[RHS]]
; CHECK: G_STORE [[SUM]](s64), [[ADDR]](p0)
define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, i64* %addr) {
@@ -240,7 +240,7 @@ define void @test_stack_slots([8 x i64], i64 %lhs, i64 %rhs, i64* %addr) {
; CHECK: G_STORE [[C12]](s64), [[C12_LOC]](p0) :: (store (s64) into stack + 8, align 1)
; CHECK: [[PTR_OFFS:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK: [[PTR_LOC:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP]], [[PTR_OFFS]](s64)
-; CHECK: G_STORE [[PTR]](p0), [[PTR_LOC]](p0) :: (store (s64) into stack + 16, align 1)
+; CHECK: G_STORE [[PTR]](p0), [[PTR_LOC]](p0) :: (store (p0) into stack + 16, align 1)
; CHECK: BL @test_stack_slots
; CHECK: ADJCALLSTACKUP 24, 0, implicit-def $sp, implicit $sp
define void @test_call_stack() {
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
index 9e690f50e247..ceb599b56cd4 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
@@ -32,7 +32,7 @@ body: |
; CHECK: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[COPY]](<2 x p0>)
- ; CHECK: G_STORE [[BITCAST]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x p0>) into %ir.ptr)
+ ; CHECK: G_STORE [[BITCAST]](<2 x s64>), [[COPY1]](p0) :: (store (<2 x s64>) into %ir.ptr)
; CHECK: RET_ReallyLR
%0:_(<2 x p0>) = COPY $q0
%1:_(p0) = COPY $x0
@@ -52,7 +52,7 @@ body: |
; CHECK-LABEL: name: load_v2p0
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x p0>) from %ir.ptr)
+ ; CHECK: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.ptr)
; CHECK: [[BITCAST:%[0-9]+]]:_(<2 x p0>) = G_BITCAST [[LOAD]](<2 x s64>)
; CHECK: $q0 = COPY [[BITCAST]](<2 x p0>)
; CHECK: RET_ReallyLR implicit $q0
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