[PATCH] D106139: [AMDGPU] Combine srl of add that intends to get the carry of the add as addcarry

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D106139#2882981 <https://reviews.llvm.org/D106139#2882981>, @foad wrote:

> This seems like a target-independent optimization that InstCombine could do on IR, using the uadd_with_overflow intrinsic.

Yes. I think this pattern can also appear as a result of legalization expansions, so could also be a generic combine



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Comment at: llvm/test/CodeGen/AMDGPU/combine-srl-add.ll:13
+  ret i64 %add.c.shr
+}
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This could use a lot more tests, like making sure the number of bits in the shift match, and that the sources are zexts. Also what if tere are multiple uses of the add?

Also should cover sub, and stress both vector and scalar versions. Does this also work with sext if the shift is ashr?


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  https://reviews.llvm.org/D106139/new/

https://reviews.llvm.org/D106139