[llvm] 5643be9 - [DAG] Enable foldSelectOfBinops on select(setcc(),binop(),binop()) calls

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-07-18T18:38:59+01:00
New Revision: 5643be96bc1fd6e8b00aa25b0bb274511d6b1100

URL: https://github.com/llvm/llvm-project/commit/5643be96bc1fd6e8b00aa25b0bb274511d6b1100
DIFF: https://github.com/llvm/llvm-project/commit/5643be96bc1fd6e8b00aa25b0bb274511d6b1100.diff

LOG: [DAG] Enable foldSelectOfBinops on select(setcc(),binop(),binop()) calls

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/test/CodeGen/AMDGPU/idiv-licm.ll
    llvm/test/CodeGen/X86/combine-shl.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 951acb6ae05e2..4f152c6218f4b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9644,11 +9644,13 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
       return SelectNode;
     }
 
-    return SimplifySelect(DL, N0, N1, N2);
+    if (SDValue NewSel = SimplifySelect(DL, N0, N1, N2))
+      return NewSel;
   }
 
-  if (SDValue BinOp = foldSelectOfBinops(N))
-    return BinOp;
+  if (!VT.isVector())
+    if (SDValue BinOp = foldSelectOfBinops(N))
+      return BinOp;
 
   return SDValue();
 }

diff  --git a/llvm/test/CodeGen/AMDGPU/idiv-licm.ll b/llvm/test/CodeGen/AMDGPU/idiv-licm.ll
index 32e4f58df884d..6f430fa4c2af8 100644
--- a/llvm/test/CodeGen/AMDGPU/idiv-licm.ll
+++ b/llvm/test/CodeGen/AMDGPU/idiv-licm.ll
@@ -128,10 +128,10 @@ define amdgpu_kernel void @urem32_invariant_denom(i32 addrspace(1)* nocapture %a
 ; GFX9-NEXT:    v_mul_lo_u32 v3, s3, v2
 ; GFX9-NEXT:    v_not_b32_e32 v2, v2
 ; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v2
-; GFX9-NEXT:    v_add_u32_e32 v3, s4, v3
-; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v3
-; GFX9-NEXT:    v_add_u32_e32 v2, s4, v2
+; GFX9-NEXT:    v_add_u32_e32 v4, s4, v3
+; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v4
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
+; GFX9-NEXT:    v_add_u32_e32 v2, s4, v2
 ; GFX9-NEXT:    s_add_u32 s4, s4, 1
 ; GFX9-NEXT:    v_subrev_u32_e32 v3, s2, v2
 ; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v2
@@ -165,15 +165,15 @@ define amdgpu_kernel void @urem32_invariant_denom(i32 addrspace(1)* nocapture %a
 ; GFX10-NEXT:    v_mul_lo_u32 v2, s5, v0
 ; GFX10-NEXT:    v_mul_hi_u32 v3, s4, v0
 ; GFX10-NEXT:    v_add_nc_u32_e32 v2, v3, v2
-; GFX10-NEXT:    v_not_b32_e32 v3, v2
-; GFX10-NEXT:    v_mul_lo_u32 v2, s3, v2
-; GFX10-NEXT:    v_mul_lo_u32 v3, s2, v3
+; GFX10-NEXT:    v_mul_lo_u32 v3, s3, v2
+; GFX10-NEXT:    v_not_b32_e32 v2, v2
+; GFX10-NEXT:    v_mul_lo_u32 v2, s2, v2
+; GFX10-NEXT:    v_add_nc_u32_e32 v4, s4, v3
+; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s2, v4
+; GFX10-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc_lo
 ; GFX10-NEXT:    v_add_nc_u32_e32 v2, s4, v2
-; GFX10-NEXT:    v_add_nc_u32_e32 v3, s4, v3
-; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s2, v2
 ; GFX10-NEXT:    s_add_u32 s4, s4, 1
 ; GFX10-NEXT:    s_addc_u32 s5, s5, 0
-; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
 ; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s2, v2
 ; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s2, v2
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo

diff  --git a/llvm/test/CodeGen/X86/combine-shl.ll b/llvm/test/CodeGen/X86/combine-shl.ll
index 9ba7943b7573d..142e03377d0db 100644
--- a/llvm/test/CodeGen/X86/combine-shl.ll
+++ b/llvm/test/CodeGen/X86/combine-shl.ll
@@ -470,12 +470,11 @@ define <4 x i32> @combine_vec_shl_ge_ashr_extact1(<4 x i32> %x) {
 define i32 @combine_shl_ge_sel_ashr_extact0(i32 %x, i32 %y, i32 %z) {
 ; CHECK-LABEL: combine_shl_ge_sel_ashr_extact0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movl %esi, %eax
-; CHECK-NEXT:    shrl $3, %edi
-; CHECK-NEXT:    shrl $3, %eax
+; CHECK-NEXT:    # kill: def $edi killed $edi def $rdi
 ; CHECK-NEXT:    testl %edx, %edx
-; CHECK-NEXT:    cmovnel %edi, %eax
-; CHECK-NEXT:    shll $5, %eax
+; CHECK-NEXT:    cmovel %esi, %edi
+; CHECK-NEXT:    leal (,%rdi,4), %eax
+; CHECK-NEXT:    andl $-32, %eax
 ; CHECK-NEXT:    retq
   %cmp = icmp ne i32 %z, 0
   %ashrx = ashr exact i32 %x, 3