[llvm] 9599567 - [DAG] SelectionDAG::MaskedElementsAreZero - assert we're calling with a vector. NFCI.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2021-07-16T17:43:35+01:00
New Revision: 95995673d1babee5731146f45ad3ce79c32f06d4

URL: https://github.com/llvm/llvm-project/commit/95995673d1babee5731146f45ad3ce79c32f06d4
DIFF: https://github.com/llvm/llvm-project/commit/95995673d1babee5731146f45ad3ce79c32f06d4.diff

LOG: [DAG] SelectionDAG::MaskedElementsAreZero - assert we're calling with a vector. NFCI.

Add an assertion that we've calling MaskedElementsAreZero with a vector op and that the DemandedElts arg is a matching width.

Makes the error a lot easier to grok when something else accidentally gets used.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index e194e1b328e6..8886a2d5f54c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2450,6 +2450,10 @@ bool SelectionDAG::MaskedValueIsZero(SDValue V, const APInt &Mask,
 /// use this predicate to simplify operations downstream.
 bool SelectionDAG::MaskedElementsAreZero(SDValue Op, const APInt &DemandedElts,
                                          unsigned Depth) const {
+  assert(Op.getValueType().isFixedLengthVector() &&
+         Op.getValueType().getVectorNumElements() ==
+             DemandedElts.getBitWidth() &&
+         "MaskedElementsAreZero vector size mismatch");
   unsigned BitWidth = Op.getScalarValueSizeInBits();
   APInt DemandedBits = APInt::getAllOnesValue(BitWidth);
   return MaskedValueIsZero(Op, DemandedBits, DemandedElts, Depth);