[PATCH] D105509: [RISCV] Teach constant materialization that it can use zext.w at the end with Zba to reduce number of instructions.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp:87
-    unsigned ShiftAmount = countLeadingZeros((uint64_t)Val);
-    Val <<= ShiftAmount;
     // Fill in the bits that will be shifted out with 1s. An example where this
----------------
luismarques wrote:
> Was this undefined behavior (shifting into the sign bit)? Thanks for fixing it :)
Stealing the text from the code that instruments for UBSan.

```
        // In C99, we are not permitted to shift a 1 bit into the sign bit.                                                                                                                                                            
        // Under C++11's rules, shifting a 1 bit into the sign bit is                                                                                                                                                                  
        // OK, but shifting a 1 bit out of it is not. (C89 and C++03 don't                                                                                                                                                             
        // define signed left shifts, so we use the C99 and C++11 rules there).
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105509/new/

https://reviews.llvm.org/D105509