[PATCH] D105509: [RISCV] Teach constant materialization that it can use zext.w at the end with Zba to reduce number of instructions.

[Luís Marques via Phabricator via llvm-commits]

luismarques accepted this revision.
luismarques added a comment.
This revision is now accepted and ready to land.

LGTM. Thanks!



================
Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp:87
-    unsigned ShiftAmount = countLeadingZeros((uint64_t)Val);
-    Val <<= ShiftAmount;
     // Fill in the bits that will be shifted out with 1s. An example where this
----------------
Was this undefined behavior (shifting into the sign bit)? Thanks for fixing it :)


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:435-440
-  bool IsRV64 = MF->getSubtarget<RISCVSubtarget>().is64Bit();
   Register SrcReg = RISCV::X0;
   Register Result = MRI.createVirtualRegister(&RISCV::GPRRegClass);
   unsigned Num = 0;
 
-  if (!IsRV64 && !isInt<32>(Val))
----------------
We might have more of these elsewhere, where we are getting the `STI` from the `MF` when we can get it more directly.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105509/new/

https://reviews.llvm.org/D105509