[llvm] f57f8f7 - GlobalISel: Remove dead function

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2021-07-16T08:59:25-04:00
New Revision: f57f8f7ccc804d0ae24541442abdd8bbc4c129cb

URL: https://github.com/llvm/llvm-project/commit/f57f8f7ccc804d0ae24541442abdd8bbc4c129cb
DIFF: https://github.com/llvm/llvm-project/commit/f57f8f7ccc804d0ae24541442abdd8bbc4c129cb.diff

LOG: GlobalISel: Remove dead function

Added: 
    

Modified: 
    llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
    llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

Removed: 
    


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diff  --git a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
index 0e6392084a50..6bdaddd9c6f5 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
@@ -363,14 +363,6 @@ class CallLowering {
                          const DataLayout &DL, CallingConv::ID CallConv,
                          SmallVectorImpl<uint64_t> *Offsets = nullptr) const;
 
-  /// Generate instructions for unpacking \p SrcReg into the \p DstRegs
-  /// corresponding to the aggregate type \p PackedTy.
-  ///
-  /// \param DstRegs should contain one virtual register for each base type in
-  ///        \p PackedTy, as returned by computeValueLLTs.
-  void unpackRegs(ArrayRef<Register> DstRegs, Register SrcReg, Type *PackedTy,
-                  MachineIRBuilder &MIRBuilder) const;
-
   /// Analyze the argument list in \p Args, using \p Assigner to populate \p
   /// CCInfo. This will determine the types and locations to use for passed or
   /// returned values. This may resize fields in \p Args if the value is split

diff  --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index a1658969ea22..83dc9bf4244b 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -242,22 +242,6 @@ void CallLowering::splitToValueTypes(const ArgInfo &OrigArg,
   SplitArgs.back().Flags[0].setInConsecutiveRegsLast();
 }
 
-void CallLowering::unpackRegs(ArrayRef<Register> DstRegs, Register SrcReg,
-                              Type *PackedTy,
-                              MachineIRBuilder &MIRBuilder) const {
-  assert(DstRegs.size() > 1 && "Nothing to unpack");
-
-  const DataLayout &DL = MIRBuilder.getDataLayout();
-
-  SmallVector<LLT, 8> LLTs;
-  SmallVector<uint64_t, 8> Offsets;
-  computeValueLLTs(DL, *PackedTy, LLTs, &Offsets);
-  assert(LLTs.size() == DstRegs.size() && "Regs / types mismatch");
-
-  for (unsigned i = 0; i < DstRegs.size(); ++i)
-    MIRBuilder.buildExtract(DstRegs[i], SrcReg, Offsets[i]);
-}
-
 /// Pack values \p SrcRegs to cover the vector type result \p DstRegs.
 static MachineInstrBuilder
 mergeVectorRegsToResultRegs(MachineIRBuilder &B, ArrayRef<Register> DstRegs,