[llvm] 09c9f4d - [AMDGPU][MC] Added missing isCall/isBranch flags

[Dmitry Preobrazhensky via llvm-commits]

Author: Dmitry Preobrazhensky
Date: 2021-07-16T14:59:10+03:00
New Revision: 09c9f4dc7db2c6f3972089c08dcfc64a5d6bc091

URL: https://github.com/llvm/llvm-project/commit/09c9f4dc7db2c6f3972089c08dcfc64a5d6bc091
DIFF: https://github.com/llvm/llvm-project/commit/09c9f4dc7db2c6f3972089c08dcfc64a5d6bc091.diff

LOG: [AMDGPU][MC] Added missing isCall/isBranch flags

Added isCall for S_CALL_B64; added isBranch for S_SUBVECTOR_LOOP_*.

Differential Revision: https://reviews.llvm.org/D106072

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SOPInstructions.td

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 7db78dac95b3..e9697017aac0 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -729,6 +729,8 @@ class SOPK_Real<bits<5> op, SOPK_Pseudo ps> :
   let SchedRW            = ps.SchedRW;
   let mayLoad            = ps.mayLoad;
   let mayStore           = ps.mayStore;
+  let isBranch           = ps.isBranch;
+  let isCall             = ps.isCall;
 
   // encoding
   bits<7>  sdst;