[PATCH] D105925: [TableGen] Warn when patterns are ignored due to impossible types

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D105925#2877311 <https://reviews.llvm.org/D105925#2877311>, @kparzysz wrote:

> Suppose that you have an architecture that can be either 32- or 64-bit with mostly the same instruction/register sets for both.  This is the kind of a scenario that this "HW mode" thing was invented for: it allows you to write a single set of patterns that will work in either mode.  However, in practice it can happen that there are instructions that don't exist in some modes.  Let's assume that this imaginary architecture has a 32-bit add instruction `ADD`, but not a 64-bit one.  Let's say that `GR` is the register class (parameterized by the 32-/64-bit hw mode).  If you write
>
>   def: Pat<(add (i32 GR:$a), (i32 GR:$b)), (ADD $a $b)>;
>
> it will be expanded into the two modes, but in the 64-bit variant it will create a contradiction, since in `(i32 GR:$a)` the `GR` class will hold `i64`.
>
> This shouldn't emit a warning by default, because in this case there is nothing to be corrected here.  In cases like that the user will always get the warning, which is not a desired behavior.

RISCV uses HW mode and has a bunch of i64 patterns that should be ignored for the 32-bit mode. Does the RISCV build produce warnings from this patch?


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